Discrete logarithms a parallel pseudorandom pattern generator analysis method Paul H. Bardell OriginalPaper Pages: 17 - 31
Counter-based compaction: An analysis for BIST Slawomir PilarskiKevin James Wiebe OriginalPaper Pages: 33 - 43
Parity bit calculation and test signal compaction for BIST applications Sungju ParkSheldon B. Akers OriginalPaper Pages: 45 - 52
The OR-k method for on-line checking of programmable logic arrays D. M. MarcynukD. M. Miller OriginalPaper Pages: 53 - 65
MT-SIM a mixed-level transition fault simulator based on parallel patterns Chung Len LeeChing Ping WuShueng Dar Hwang OriginalPaper Pages: 67 - 78
Fault simulation on massively parallel SIMD machines algorithms, implementations and results Vinod NarayananVijay Pitchumani OriginalPaper Pages: 79 - 92
Test quality of hierarchical defect-tolerant integrated circuits Claude ThibeaultYvon SavariaJean -Louis Houle OriginalPaper Pages: 93 - 102
