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Field-Programmable Logic and Applications

11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 Proceedings

  • Conference proceedings
  • © 2001

Overview

Editors:
  1. Gordon Brebner

    1. Division of Informatics, University of Edinburgh, Edinburgh, UK

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  2. Roger Woods

    1. School of Electrical and Electronic Engineering, Queen’s University of Belfast, Belfast, UK

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    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 2147)

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Table of contents (74 papers)

  1. DSP 2

    1. Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders

      • Shervin Sheidaei, Hamid Noori, Ahmad Akbari, Hosein Pedram
      Pages 388-397

  2. Loops and Systolic

    1. Loop Tiling for Reconfigurable Accelerators

      • Steven Derrien, Sanjay Rajopadhye
      Pages 398-408

    2. The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems

      • Gilles Sassatelli, Lionel Torres, Jerome Galy, Gaston Cambon, Camille Diou
      Pages 409-419

    3. A n-Bit Reconfigurable Scalar Quantiser

      • Oswaldo Cadenas, Graham Megson
      Pages 420-429

  5. Runtime Reconfiguration 2

    1. Dynamically Reconfigurable Cores

      • John MacBeth, Patrick Lysaght
      Pages 462-472

    2. Reconfigurable Breakpoints for Co-debug

      • Tim Price, Cameron Patterson
      Pages 473-482

  6. Faults

    1. Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification

      • Timothy Wheeler, Paul Graham, Brent Nelson, Brad Hutchings
      Pages 483-492

    2. FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits

      • Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
      Pages 493-502

  7. Methodology 2

    1. A Generic Library for Adaptive Computing Environments

      • Tilman Neumann, Andreas Koch
      Pages 503-512

    2. Generative Development System for FPGA essors with Active Components

      • Stephan RĂĽhl, Peter Dillinger, Stefan Hezel, Reinhard Männer
      Pages 513-522

    3. Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines

      • JoĂŁo M. P. Cardoso, Horácio C. Neto
      Pages 523-533

    4. System Level Tools for DSP in FPGAs

      • James Hwang, Brent Milne, Nabeel Shirazi, Jeffrey D. Stroomer
      Pages 534-543

  8. Arithmetic

    1. Parameterized Function Evaluation for FPGAs

      • Oskar Mencer, Nicolas Boullis, Wayne Luk, Henry Styles
      Pages 544-554

    2. Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures

      • Michael J. Wirthlin, Brian McMurtrey
      Pages 555-564

    3. A Digit-Serial Structure for Reconfigurable Multipliers

      • Chakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk
      Pages 565-573

    4. FPGA Resource Reduction Through Truncated Multiplication

      • Kent E. Wires, Michael J. Schulte, Don McCarley
      Pages 574-583
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Keywords

Editors and Affiliations

  • Division of Informatics, University of Edinburgh, Edinburgh, UK

    Gordon Brebner

  • School of Electrical and Electronic Engineering, Queen’s University of Belfast, Belfast, UK

    Roger Woods

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