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ASIC Design and Synthesis

RTL Design Using Verilog

Authors: Taraate, Vaibbhav

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  • Unique to interpretation of ASIC design using Verilog
  • Practical ASIC design scenarios and issues and helpful to professionals
  • More than 150 practical examples for ASIC design, Synthesis and timing analysis
  • Key case studies in the generic form and design synthesis and timing closure for ASIC
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eBook $149.00
price for USA in USD
  • ISBN 978-981-334-642-0
  • Digitally watermarked, DRM-free
  • Included format: EPUB, PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $199.99
price for USA in USD
  • ISBN 978-981-334-641-3
  • Free shipping for individuals worldwide
  • Institutional customers should get in touch with their account manager
  • Covid-19 shipping restrictions
  • Usually ready to be dispatched within 3 to 5 business days, if in stock
About this book

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.

About the authors

Vaibbhav Taraate is an entrepreneur and mentor at “1 Rupee S T”. He holds B.E. (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology (IIT) Bombay, India, in 1999. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog , VHDL and SystemVerilog. He has worked with multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis and optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.


Table of contents (20 chapters)

Table of contents (20 chapters)

Buy this book

eBook $149.00
price for USA in USD
  • ISBN 978-981-334-642-0
  • Digitally watermarked, DRM-free
  • Included format: EPUB, PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $199.99
price for USA in USD
  • ISBN 978-981-334-641-3
  • Free shipping for individuals worldwide
  • Institutional customers should get in touch with their account manager
  • Covid-19 shipping restrictions
  • Usually ready to be dispatched within 3 to 5 business days, if in stock
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Bibliographic Information

Bibliographic Information
Book Title
ASIC Design and Synthesis
Book Subtitle
RTL Design Using Verilog
Authors
Copyright
2021
Publisher
Springer Singapore
Copyright Holder
Springer Nature Singapore Pte Ltd.
eBook ISBN
978-981-334-642-0
DOI
10.1007/978-981-33-4642-0
Hardcover ISBN
978-981-334-641-3
Edition Number
1
Number of Pages
XXI, 330
Number of Illustrations
127 b/w illustrations, 184 illustrations in colour
Topics