VLSI Design and Test

Flexible Adaptive FIR Filter Designs Using LMS Algorithm

Pages 61-71

Mohamed Asan Basiri, M.

An Efficient Test and Fault Tolerance Technique for Paper-Based DMFB

Pages 72-86

Das, Chandan (et al.)

A Generalized Technique of Automated Pin Sharing on Hexagonal Electrode Based Digital Microfluidic Biochip Along with Its Design Methodology

Pages 87-101

Dutta, Amartya (et al.)

A Space Efficient Greedy Droplet Routing for Digital Microfluidics Biochip

Pages 102-114

Swain, Jyotiranjan (et al.)

Design of 635 MHz Bandpass Filter Using High-Q Floating Active Inductor

Pages 115-125

Hota, Aditya Kumar (et al.)

Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology

Pages 126-140

Siddamal, Saroja V. (et al.)

Clock Pulse Based Foreground Calibration of a Sub-Radix-2 Successive Approximation Register ADC

Pages 141-149

Mahendra Reddy, M. (et al.)

Approximate Computing Based Adder Design for DWT Application

Pages 150-163

Acharya, Moumita (et al.)

An Efficient Wireless Charging Technique Using Inductive and Resonant Circuits

Pages 164-170

Agrawal, Purvi (et al.)

A Novel Gate-Level On-Chip Crosstalk Noise Reduction Circuit for Deep Sub-micron Technology

Pages 171-179

Majumdar, Swatilekha

On-Chip Threshold Compensated Voltage Doubler for RF Energy Harvesting

Pages 180-189

Mohan, Arun (et al.)

Utilizing NBTI for Operation Detection of Integrated Circuits

Pages 190-201

Shah, Ambika Prasad (et al.)

A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS

Pages 202-214

Kammari, Raviteja (et al.)

A CMOS Low Noise Amplifier with Improved Gain

Pages 215-223

Ambulker, Sunanda (et al.)

Radiation Hardened by Design Sense Amplifier

Pages 224-235

Verma, Avinash (et al.)

Delay Efficient All Optical Carry Lookahead Adder

Pages 236-244

Roy, Sayantani (et al.)

Asynchronous Hardware Design for Floating Point Multiply-Accumulate Circuit

Pages 247-257

Mohamed Asan Basiri, M.

A Unified Methodology for Hardware Obfuscation and IP Watermarking

Pages 258-271

Gangurde, Saurabh (et al.)

Threshold Implementation of a Low-Cost CLEFIA-128 Cipher for Power Analysis Attack Resistance

Pages 272-285

Shanthi Rekha, S. (et al.)

Brain Inspired One Shot Learning Method for HD Computing

Pages 286-297

Nair, Devika R. (et al.)

Dual-Edge Triggered Lightweight Implementation of AES for IoT Security

Pages 298-307

Khan, Sajid (et al.)

2L-2D Routing for Buffered Mesh Network-on-Chip

Pages 308-320

Kunthara, Rose George (et al.)

Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural Network

Pages 321-333

Raut, Gopal (et al.)

An Ultra Low Power AES Architecture for IoT

Pages 334-344

Khan, Sajid (et al.)

Efficient Closely-Coupled Integration of AES Coprocessor with LEON3 Processor

Pages 345-356

Bansal, Rajul (et al.)

Investigating the Role of Parasitic Resistance in a Class of Nanoscale Interconnects

Pages 357-370

Yousuf, Shah Zahid (et al.)

A True Single-Phase Error Masking Flip-Flop with Reduced Clock Power for Near-Threshold Designs

Pages 371-382

Sharma, Priyamvada (et al.)

ASIC Based LVDT Signal Conditioner for High-Accuracy Measurements

Pages 385-397

Raghunath, K. P. (et al.)

Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard

Pages 398-412

Arya, Neelam (et al.)

Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods

Pages 413-427

Vineesh, V. S. (et al.)

Comparative Analysis of Logic Gates Based on Spin Transfer Torque (STT) and Differential Spin Hall Effect (DSHE) Switching Mechanisms

Pages 428-441

Tankwal, Piyush (et al.)

Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture

Pages 442-454

Veda Bhanu, P. (et al.)

A Realistic Configurable Level Triggered Flip-Flop in Quantum-Dot Cellular Automata

Pages 455-467

Goswami, Mrinal (et al.)

User Guided Register Manipulation in Digital Circuits

Pages 468-481

Panigrahi, Priyanka (et al.)

RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor

Pages 482-495

Raveendran, Aneesh (et al.)

Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU

Pages 496-509

Raveendran, Aneesh (et al.)

Real Time Implementation of Convolutional Neural Network to Detect Plant Diseases Using Internet of Things

Pages 510-522

Bajpai, Govind (et al.)

A Novel 20nm FinFET Based 10T SRAM Cell Design for Improved Performance

Pages 523-531

Singh, Anushka (et al.)

Design of a Power Efficient Pulse Latch Circuit as a Solution for Master Slave Flip-Flop

Pages 532-540

Sulthan, Muneeb (et al.)

Design and Analysis for Power Reduction with High SNM of 10T SRAM Cell

Pages 541-549

Singh, Kamini (et al.)

A CMOS/MTJ Based Novel Non-volatile SRAM Cell with Asynchronous Write Termination for Normally OFF Applications

Pages 553-564

Monga, Kanika (et al.)

Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression Models

Pages 565-578

Amuru, Deepthi (et al.)

A Novel Design of SRAM Using Memristors at 45 nm Technology

Pages 579-589

Jeffry Louis, V. (et al.)

Design and Calibration of 14-bit 10 KS/s Low Power SAR ADC for Bio-medical Applications

Pages 590-604

Mekkattillam, Yadukrishnan (et al.)

An Approach for Detection of Node Displacement Fault (NDF) in Reversible Circuit

Pages 605-616

Mondal, Bappaditya (et al.)

Novel Approach for Improved Signal Integrity and Power Dissipation Using MLGNR Interconnects

Pages 617-629

Kumbhare, Vijay Rao (et al.)

A Robust Low-Power Write-Assist Data-Dependent-Power-Supplied 12T SRAM Cell

Pages 630-642

Gupta, Neha (et al.)

Low Leakage Highly Stable Robust Ultra Low Power 8T SRAM Cell

Pages 643-654

Gupta, Neha (et al.)

Compact Spiking Neural Network System with SiGe Based Cylindrical Tunneling Transistor for Low Power Applications

Pages 655-663

Beohar, Ankur (et al.)

Compact Modeling of Drain-Extended MOS Transistor Using BSIM-BULK Model

Pages 667-678

Parihar, Shivendra Singh (et al.)

Technology Characterization Model and Scaling for Energy Management

Pages 679-693

Goyal, Harshil (et al.)

GaAs-SiGe Based Novel Device Structure of Doping Less Tunnel FET

Pages 694-701

Yadav, Shivendra (et al.)

Performance Modelling and Dynamic Scheduling on Heterogeneous-ISA Multi-core Architectures

Pages 702-715

Boran, Nirmal Kumar (et al.)

Simulation Study of III-V Lateral Tunnel FETs with Gate-Drain Underlap

Pages 716-726

Yempada, Venkata Appa Rao (et al.)

Low-Voltage Dual-Gate Organic Thin Film Transistors with Distinctly Placed Source and Drain

Pages 727-738

Pal, Shagun (et al.)

A Latency and Throughput Efficient Successive Cancellation Decoding of Polar Codes

Pages 741-748

Manasa, Sistla Lakshmi (et al.)

All-Digital CMOS On-Chip Temperature Sensor with Time-Assisted Analytical Model

Pages 749-763

Pokhara, Ankur (et al.)

Intelligent Traffic Light Controller: A Solution for Smart City Traffic Problem

Pages 764-772

Sabir, Anam (et al.)