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VLSI Design and Test

23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019, Revised Selected Papers

  • Conference proceedings
  • © 2019

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Editors:
  1. Anirban Sengupta

    1. Computer Science and Engineering, Indian Institute of Technology Indore, Indore, India

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  2. Sudeb Dasgupta

    1. Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, India

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  3. Virendra Singh

    1. Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India

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  4. Rohit Sharma

    1. Department of Electrical Engineering, Indian Institute of Technology Ropar, Rupnagar, India

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  5. Santosh Kumar Vishvakarma

    1. Electrical Engineering, Indian Institute of Technology Indore, Indore, India

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Part of the book series: Communications in Computer and Information Science (CCIS, volume 1066)

Included in the following conference series:

Conference proceedings info: VDAT 2019.

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Table of contents (63 papers)

  1. Front Matter

    Pages i-xvi
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  2. Analog and Mixed Signal Design

    1. Front Matter

      Pages 1-1
      Download chapter PDF

    2. Automations and Methodologies for Efficient and Quality Conscious Analog Layout Implementation

      • Varun Kumar Dwivedi, Madhvi Sharma, Chandaka Venu
      Pages 3-13

    3. A 2.4 GHz High Efficiency Capacitive Cross Coupled Common Gate Class-E Differential Power Amplifier

      • Archana Sunitha, Bhaskar Manickam
      Pages 14-22

    4. A 1.25–20 GHz Wide Tuning Range Frequency Synthesis for 40-Gb/s SerDes Application

      • Javed S. Gaggatur, Abhishek Chaturvedi
      Pages 23-35

    5. Analyzing Design Parameters of Nano-Magnetic Technology Based Converter Circuit

      • Bandan Kumar Bhoi, Neeraj Kumar Misa, Shailesh Singh Chouhan, Sarthak Acharya
      Pages 36-46

    6. Design of Current Mode Sigmoid Function and Hyperbolic Tangent Function

      • Debanjana Datta, Sweta Agarwal, Vikash Kumar, Mayank Raj, Baidyanath Ray, Ayan Banerjee
      Pages 47-60

    7. Flexible Adaptive FIR Filter Designs Using LMS Algorithm

      • M. Mohamed Asan Basiri
      Pages 61-71

    8. An Efficient Test and Fault Tolerance Technique for Paper-Based DMFB

      • Chandan Das, Sarit Chakraborty, Susanta Chakraborty
      Pages 72-86

    9. A Generalized Technique of Automated Pin Sharing on Hexagonal Electrode Based Digital Microfluidic Biochip Along with Its Design Methodology

      • Amartya Dutta, Riya Majumder, Debasis Dhal, Rajat Kumar Pal
      Pages 87-101

    10. A Space Efficient Greedy Droplet Routing for Digital Microfluidics Biochip

      • Jyotiranjan Swain, Kolluri Rajesh, Sumanta Pyne
      Pages 102-114

    11. Design of 635 MHz Bandpass Filter Using High-Q Floating Active Inductor

      • Aditya Kumar Hota, Kabiraj Sethi
      Pages 115-125

    12. Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology

      • Saroja V. Siddamal, Suhas B. Shirol, Shraddha Hiremath, Nalini C. Iyer
      Pages 126-140

    13. Clock Pulse Based Foreground Calibration of a Sub-Radix-2 Successive Approximation Register ADC

      • M. Mahendra Reddy, Sounak Roy
      Pages 141-149

    14. Approximate Computing Based Adder Design for DWT Application

      • Moumita Acharya, Samik Basu, Biranchi Narayan Behera, Amlan Chakrabarti
      Pages 150-163

    15. An Efficient Wireless Charging Technique Using Inductive and Resonant Circuits

      • Purvi Agrawal, Ruchi Dhamnani, Ananya Garg, Shrivishal Tripathi, Manoj Kumar Majumder
      Pages 164-170

    16. A Novel Gate-Level On-Chip Crosstalk Noise Reduction Circuit for Deep Sub-micron Technology

      • Swatilekha Majumdar
      Pages 171-179

    17. On-Chip Threshold Compensated Voltage Doubler for RF Energy Harvesting

      • Arun Mohan, Saroj Mondal, Surya Shankar Dan
      Pages 180-189

    18. Utilizing NBTI for Operation Detection of Integrated Circuits

      • Ambika Prasad Shah, Amirhossein Moshrefi, Michael Waltl
      Pages 190-201

    19. A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS

      • Raviteja Kammari, Vijaya Sankara Rao Pasupureddi
      Pages 202-214
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  1. VLSI Design and Test

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About this book

This book constitutes the refereed proceedings of the 23st International Symposium on VLSI Design and Test, VDAT 2019, held in Indore, India, in July 2019.

The 63 full papers were carefully reviewed and selected from 199 submissions. The papers are organized in topical sections named: analog and mixed signal design; computing architecture and security; hardware design and optimization; low power VLSI and memory design; device modelling; and hardware implementation.

Editors and Affiliations

  • Computer Science and Engineering, Indian Institute of Technology Indore, Indore, India

    Anirban Sengupta

  • Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, India

    Sudeb Dasgupta

  • Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India

    Virendra Singh

  • Department of Electrical Engineering, Indian Institute of Technology Ropar, Rupnagar, India

    Rohit Sharma

  • Electrical Engineering, Indian Institute of Technology Indore, Indore, India

    Santosh Kumar Vishvakarma

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