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Fan-Out Wafer-Level Packaging

Authors: Lau, John H.

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  • Addresses fan-out wafer-level packaging (FOWLP), in theory and particularly in engineering practice
  •  Studies in detail FOWLP design, materials, processes, fabrication, and reliability assessments 
  • Presents the latest research and development findings, offering a “one-stop” guide to the state of the art of FOWLP
  • Provides the first comprehensive and in-depth guide to FOWLP
  • Offers cutting-edge information on the most important new developments in electronic packaging for microelectronics
  •  
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eBook $84.99
price for USA in USD
  • ISBN 978-981-10-8884-1
  • Digitally watermarked, DRM-free
  • Included format: EPUB, PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $149.99
price for USA in USD
  • ISBN 978-981-10-8883-4
  • Free shipping for individuals worldwide
  • Immediate ebook access, if available*, with your print order
  • Usually dispatched within 3 to 5 business days.
Softcover $109.99
price for USA in USD
  • ISBN 978-981-13-4266-0
  • Free shipping for individuals worldwide
  • Immediate ebook access, if available*, with your print order
  • Usually dispatched within 3 to 5 business days.
About this book

This comprehensive guide to fan-out wafer-level packaging (FOWLP) technology compares FOWLP with flip chip and fan-in wafer-level packaging. It presents the current knowledge on these key enabling technologies for FOWLP, and discusses several packaging technologies for future trends. The Taiwan Semiconductor Manufacturing Company (TSMC) employed their InFO (integrated fan-out) technology in A10, the application processor for Apple’s iPhone, in 2016, generating great excitement about FOWLP technology throughout the semiconductor packaging community. For many practicing engineers and managers, as well as scientists and researchers, essential details of FOWLP – such as the temporary bonding and de-bonding of the carrier on a reconstituted wafer/panel, epoxy molding compound (EMC) dispensing, compression molding, Cu revealing, RDL fabrication, solder ball mounting, etc. – are not well understood. 

Intended to help readers learn the basics of problem-solving methods and understand the trade-offs inherent in making system-level decisions quickly, this book serves as a valuable reference guide for all those faced with the challenging problems created by the ever-increasing interest in FOWLP, helps to remove roadblocks, and accelerates the design, materials, process, and manufacturing development of key enabling technologies for FOWLP.

About the authors

SPECIALIZED PROFESSIONAL COMPETENCE

Design, analysis, materials, process, manufacturing, qualification, reliability, testing, and thermal management of electronic and optoelectronic components and systems. SMT, fan-out/fan-in WLP, TSV, 3D IC Integration, heterogeneous integration and SiP. Leadfree soldering, manufacturing, and solder joint reliability. Management of a R&D Laboratory and Company.

BACKGROUND AND PROFESSIONAL EXPERIENCE

Ph.D.  (Theoretical and Applied Mechanics), University of Illinois, Urbana, IL (1977)

M.S.   (Engineering Physics), University of Wisconsin, Madison, WI (1974)

M.S.   (Structural Mechanics), University of British Columbia, Vancouver, BC (1973)

M.S.   (Management Science), Fairleigh Dickinson University, Teaneck, NJ (1981)

B.S.   (Civil Engineering), National Taiwan University, Taipei, Taiwan (1970)

 

ASM Pacific Technology (Sr. Technical Advisor), Hong Kong, July 2014 - Present

Industrial Technology Research Institute (ITRI Fellow), Taiwan, Jan 2010 – June 2014

Hong Kong University of Science & Technology (Visiting Professor), Jan 2009 – Jan 2010

Institute of Microelectronic, (Director, System Packaging Lab), Singapore, 2006 - Jan 2009

Agilent Technologies, Inc. (Sr. Interconnection Specialist), Santa Clara, CA, 2000-2006

Express Packaging Systems, Inc., (President), Palo Alto, CA, 1995-2000

Hewlett-Packard Labs/Company (Senior MTS/Individual Contributor), Palo Alto, CA, 1984-1995

Sandia National Laboratories (Member of Technical Staff), Albuquerque, NM, 1982-1983

Bechtel Power Corporation (Lead Engineer), San Francisco, CA, 1981-1982

Ebasco (Lead Engineer), New York, NY, 1978-1980

Exxon Production and Research Company (Research Engineer), Houston, TX, 1977-1978

 

Editorial Board of ASME Transactions, Journal of Electronic Packaging, 1989-1999

Editorial Board of IEEE Transactions on Components, Packaging, Manufacture Technology, 1990-1995

Editor-in-Chief, Circuit World, 1998-2000.

Program Chair ('90) to General Chair ('92) of the IEEE/CPMT IEMTS

Program Chair ('93) to General Chair ('95) of the IEEE/CPMT ECTC

Publication Chair for IEEE/ECTC

Symposium Organizer/Chair of the ASME Winter Annual Meeting, 1987-2002

ASME Distinguish Lecturer (2000-2003), IEEE/CPMT Distinguish Lecturer (1998-present)

 

ASME Worcester Reed Warner Medal (2015)

IEEE Components Packaging and Manufacturing Technology Field Award (2013)

IMAPS William Ashman Achievement Award (2013)

Pan Wen Yuan Distinguished Research Award (2011)

IEEE/CPMT Outstanding Sustained Technical Contribution Award (2010)

Best IEEE Transactions Paper Award (2010 Components Packaging and Manufacturing Technology)

Outstanding Paper Award (2009 IEEE EPTC)

SME Total Excellence in Electronics Manufacturing Award (2001)

Best ASME Transactions Paper Award (2000 Journal of Electronic Packaging)

IEEE/CPMT Outstanding Contribution Awards (2000)

IEEE Meritorious Achievement Award in Continuing Education (2000)   

ASME/EEP Technical Achievement Award (1998)

IEEE/CPMT Manufacturing Awards (1994)

Best of Conference Paper Award (1989 IEEE ECTC)

IEEE Fellow (since 1994), ASME Fellow (since 1999), IMAPS Fellow (since 2013)

Over 20 books, 450 peer-reviewed papers, 30 issued and pending patents, and 290 keynotes/lectures.

Reviews

“This is a unique book written by well known & distinguished expert Dr. John Lau … reading this book will be an eye-opening journal to all who want to truly understand fan-out wafer level packaging. You will find so many details and state-of-the-art information in this book. … I consider this is an excellent book with great value either to read or as a reference resource, and definitely I will strongly recommend it to my colleagues and friends.” (Yong Liu, Amazon.com, June, 2018) 

Table of contents (11 chapters)

Table of contents (11 chapters)

Buy this book

eBook $84.99
price for USA in USD
  • ISBN 978-981-10-8884-1
  • Digitally watermarked, DRM-free
  • Included format: EPUB, PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $149.99
price for USA in USD
  • ISBN 978-981-10-8883-4
  • Free shipping for individuals worldwide
  • Immediate ebook access, if available*, with your print order
  • Usually dispatched within 3 to 5 business days.
Softcover $109.99
price for USA in USD
  • ISBN 978-981-13-4266-0
  • Free shipping for individuals worldwide
  • Immediate ebook access, if available*, with your print order
  • Usually dispatched within 3 to 5 business days.
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Bibliographic Information

Bibliographic Information
Book Title
Fan-Out Wafer-Level Packaging
Authors
Copyright
2018
Publisher
Springer Singapore
Copyright Holder
Springer Nature Singapore Pte Ltd.
eBook ISBN
978-981-10-8884-1
DOI
10.1007/978-981-10-8884-1
Hardcover ISBN
978-981-10-8883-4
Softcover ISBN
978-981-13-4266-0
Edition Number
1
Number of Pages
XX, 303
Number of Illustrations
52 b/w illustrations, 226 illustrations in colour
Topics

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