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Microelectronic Interconnections and Assembly

  • Book
  • © 1998

Overview

Editors:
  1. George Harman

    1. Semiconductor Electronics Division, National Institute of Standards and Technology, Gaithersburg, USA

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    You can also search for this editor in PubMed   Google Scholar

  2. Pavel Mach

    1. Department of Electrotechnology, Czech Technical University in Prague, Prague, Czech Republic

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

Part of the book series: NATO Science Partnership Subseries: 3 (ASHT, volume 54)

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Table of contents (31 chapters)

  1. Front Matter

    Pages i-xiv
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  2. Packaging and Interconnection Trends - Present and Future

    1. The Packaging & Interconnection Trends in the Nordic Microelectronics Industry

      • Søren Nørlyng
      Pages 1-7

    2. IC Packaging for Miniaturised Consumer Electronics

      • Co van Veen
      Pages 9-12

    3. The Move Towards Further Miniaturisation

      • M. G. Sage
      Pages 13-19

    4. Plastic Packaging is Highly Reliable

      • Nihal Sinnadurai
      Pages 21-32

    5. Thermal Simulation and Characterization of Single Chip Packages

      • Orla Slattery, Ciaran Cahill, John Barrett, Martin O’Flaherty, Kenneth Rodgers
      Pages 33-43

    6. Current Trends and Future Issues in Solderability

      • Gary J. Ewell
      Pages 45-51

  3. Solder and Flip Chip Interconnections and Assembly

    1. The At-Temperature Mechanical Properties of Lead-Tin Based Alloys

      • W. Kinzy Jones, Y. Q. Liu, Marc A. Zampino, Gerardo L. Gonzalez
      Pages 53-58

    2. Flip Chip Technology: Is It Time of Mass Production?

      • Carlo Cognetti
      Pages 59-75

    3. Flip-Chip - The Ultimate Solution Comparing Flip-Chip and Chip Scale Packaging

      • Bill Brox, Katarina Boustedt
      Pages 77-77

    4. Solder and Solderless Flip Chip Assembly on a MCM-D in a BGA Package

      • Peter Bodo, Hans Hentzell, Jan Strandberg, Joacim Haglund, Sima Valizadeh
      Pages 79-79

    5. Solder Bumping for Flip Chip Interconnections

      • P. Annala, J. Kaitila, J. Salonen, I. Suni
      Pages 81-86

    6. Reliability of Solder Joint Interconnections in Thermally Matched Assemblies

      • E. Suhir
      Pages 87-96

    7. Mechanical Stress in Microelectronic Interconnects

      • Peter J. Gielisse, Meirong Tu, Dongming Y. White, Yang Xu Famu-Fsu
      Pages 97-108

  4. Single Chip Interconnection and Qualification: Wire Bonding and TAB

    1. Low Cost Interconnection Technology for Fast Prototyping of Multichip Modules

      • Zsolt Illyefalvi-Vitéz, János Pinkola, László Gál, Endre Tóth
      Pages 109-117

    2. Opto-Electronic Multi-Chip Modules (OE-MCMs): Current R&D and Applications to Microelectronic Interconnections

      • Sayan D. Mukherjee
      Pages 119-140

    3. On Thin Film MCM-D Interconnects

      • J. Roggen, E. Beyne, C. Truzzi, E. Ringoot, P. Pieters
      Pages 141-144

  5. Multichip Module Interconnections and Assembly I

    1. VLSI Interconnection by Bumpless TAB

      • Gérard Dehaine, Patrick Courant, Karel Kurzweil
      Pages 145-155

    2. Critical Issues in Wire-Bonded Chip Interconnections to the Year 2001

      • George G. Harman
      Pages 157-165

    3. Bonding of Al Wires to Copper Contacts on PCBs and Alumina Substrates - a Comparative Study

      • MichaÅ‚ Cież
      Pages 167-177
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About this book

MICROELECTRONIC INTERCONNECTIONS AND MICROASSEMBL Y WORKSHOP 18-21 May 1996, Prague, Czech Republic Conference Organizers: George Harman, NIST (USA) and Pavel Mach (Czech Republic) Summary of the Technical Program Thirty two presentations were given in eight technical sessions at the Workshop. A list of these sessions and their chairpersons is attached below. The Workshop was devoted to the technical aspects of advanced interconnections and microassembly, but also included papers on the education issues required to prepare students to work in these areas. In addition to new technical developments, several papers presented overviews predicting the future directions of these technologies. The basic issue is that electronic systems will continue to be miniaturized and at the same time performance must continue to improve. Various industry roadmaps were discussed as well as new smaller packaging and interconnection concepts. The newest chip packages are often based on the selection of an appropriate interconnection method. An example is the chip-scale package, which has horizontal (x-y) dimensions,;; 20% larger than the actual silicon chip itself. The chip is often flip-chip connected to a micro ball-grid-array, but direct chip attach was described also. Several papers described advances in the manufacture of such packages.

Editors and Affiliations

  • Semiconductor Electronics Division, National Institute of Standards and Technology, Gaithersburg, USA

    George Harman

  • Department of Electrotechnology, Czech Technical University in Prague, Prague, Czech Republic

    Pavel Mach

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