Lecture Notes in Electrical Engineering

Network-on-Chip Architectures

A Holistic Design Exploration

Authors: Nicopoulos, Chrysostomos, Narayanan, Vijaykrishnan, Das, Chita R.

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  • A comprehensive study of Network-on-Chip architectures for multi-core chips
  • Analysis of complex interplay between various design evaluation metrics
  • Detailed look at both macro- and micro-architectural design issues
  • Innovative solutions for increased reliability and process variability tolerance
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About this book

The continuing reduction of feature sizes into the nanoscale regime has led to dramatic increases in transistor densities. Integration at these levels has highlighted the criticality of the on-chip interconnects. Network-on-Chip (NoC) architectures are viewed as a possible solution to burgeoning global wiring delays in many-core chips, and have recently crystallized into a significant research domain. On-chip networks instill a new flavor to communication research due to their inherently resource-constrained nature. Despite the lightweight character demanded of the NoC components, modern designs require ultra-low communication latencies in order to cope with inflating data bandwidths. The work presented in Network-on-Chip Architectures addresses these issues through a comprehensive exploration of the design space. The design aspects of the NoC are viewed through a penta-faceted prism encompassing five major issues: (1) performance, (2) silicon area consumption, (3) power/energy efficiency, (4) reliability, and (5) variability. These five aspects serve as the fundamental design drivers and critical evaluation metrics in the quest for efficient NoC implementations. The research exploration employs a two-pronged approach: (a) MICRO-architectural innovations within the major NoC components, and (b) MACRO-architectural choices aiming to seamlessly merge the interconnection backbone with the remaining system modules. These two research threads and the aforementioned five key metrics mount a holistic and in-depth attack on most issues surrounding the design of NoCs in multi-core architectures.

Table of contents (11 chapters)

Table of contents (11 chapters)
  • Introduction

    Pages 1-12

    Nicopoulos, Chrysostomos (et al.)

  • A Baseline NoC Architecture

    Pages 13-16

    Nicopoulos, Chrysostomos (et al.)

  • ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39]

    Pages 19-40

    Nicopoulos, Chrysostomos (et al.)

  • RoCo: The Row–Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40]

    Pages 41-64

    Nicopoulos, Chrysostomos (et al.)

  • Exploring FaultoTolerant Network-on-Chip Architectures [37]

    Pages 65-92

    Nicopoulos, Chrysostomos (et al.)

Buy this book

eBook $119.00
price for USA in USD
  • ISBN 978-90-481-3031-3
  • Digitally watermarked, DRM-free
  • Included format: PDF, EPUB
  • Immediate eBook download after purchase and usable on all devices
  • Bulk discounts available
Hardcover $199.99
price for USA in USD
Softcover $159.99
price for USA in USD
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Bibliographic Information

Bibliographic Information
Book Title
Network-on-Chip Architectures
Book Subtitle
A Holistic Design Exploration
Authors
Series Title
Lecture Notes in Electrical Engineering
Series Volume
45
Copyright
2010
Publisher
Springer Netherlands
Copyright Holder
Springer Science+Business Media B.V.
eBook ISBN
978-90-481-3031-3
DOI
10.1007/978-90-481-3031-3
Hardcover ISBN
978-90-481-3030-6
Softcover ISBN
978-94-007-3049-6
Series ISSN
1876-1100
Edition Number
1
Number of Pages
XXII, 223
Topics