VLSI Chip Design with the Hardware Description Language VERILOG

An Introduction Based on a Large RISC Processor Design

Authors: Golze, Ulrich

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  • ISBN 978-3-642-61001-1
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About this book

This book introduces to modern design of large chips. A powerful RISC processor in the range of a SPARC is apecified in a hardware description language (HDL), it is developed hierarchically and is finally sent as a gate model to the silicon vendor LSI Logic for production. The resulting processor on a semi-custom gate-array chip with more than 50.000 used gates and an efficiency of up to 40 MIPS is tested on an automatic test equipment and a testboard. The book also introduces thoroughly to the HDL VERILOG. The included disk contains more than 40 small and medium sized executable VERILOG examples, the large processor models and the VERILOG simulator VeriWell running on PC or SPARC.

Table of contents (11 chapters)

Table of contents (11 chapters)

Buy this book

eBook $79.99
price for USA in USD
  • ISBN 978-3-642-61001-1
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Softcover $99.99
price for USA in USD
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Bibliographic Information

Bibliographic Information
Book Title
VLSI Chip Design with the Hardware Description Language VERILOG
Book Subtitle
An Introduction Based on a Large RISC Processor Design
Authors
Copyright
1996
Publisher
Springer-Verlag Berlin Heidelberg
Copyright Holder
Springer-Verlag Berlin Heidelberg
eBook ISBN
978-3-642-61001-1
DOI
10.1007/978-3-642-61001-1
Softcover ISBN
978-3-642-64650-8
Edition Number
1
Number of Pages
XIV, 360
Number of Illustrations
37 b/w illustrations
Topics