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Cryptographic Hardware and Embedded Systems -- CHES 2011

13th International Workshop, Nara, Japan, September 28 -- October 1, 2011, Proceedings

  • Conference proceedings
  • © 2011

Overview

Editors:
  1. Bart Preneel

    1. Department of Electrical Engineering - COSIC, Katholieke Universiteit Leuven and IBBT, Leuven-Heverlee, Belgium

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  2. Tsuyoshi Takagi

    1. Institute of Mathematics for Industry, Kyushu University, Fukuoka, Japan

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 6917)

Part of the book sub series: Security and Cryptology (LNSC)

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Conference proceedings info: CHES 2011.

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Table of contents (33 papers)

  1. Front Matter

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  2. FPGA Implementation

    1. An Exploration of Mechanisms for Dynamic Cryptographic Instruction Set Extension

      • Philipp Grabher, Johann Großschädl, Simon Hoerder, Kimmo Järvinen, Dan Page, Stefan Tillich et al.
      Pages 1-16

    2. FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control

      • Mehrdad Majzoobi, Farinaz Koushanfar, Srinivas Devadas
      Pages 17-32

    3. Generic Side-Channel Countermeasures for Reconfigurable Devices

      • Tim Güneysu, Amir Moradi
      Pages 33-48

  3. AES

    1. Improved Collision-Correlation Power Analysis on First Order Protected AES

      • Christophe Clavier, Benoit Feix, Georges Gagnerot, Mylène Roussellet, Vincent Verneuil
      Pages 49-62

    2. Higher-Order Glitches Free Implementation of the AES Using Secure Multi-party Computation Protocols

      • Emmanuel Prouff, Thomas Roche
      Pages 63-78

    3. Protecting AES with Shamir’s Secret Sharing Scheme

      • Louis Goubin, Ange Martinelli
      Pages 79-94

    4. A Fast and Provably Secure Higher-Order Masking of AES S-Box

      • HeeSeok Kim, Seokhie Hong, Jongin Lim
      Pages 95-107

  4. Elliptic Curve Cryptosystems

    1. Software Implementation of Binary Elliptic Curves: Impact of the Carry-Less Multiplier on Scalar Multiplication

      • Jonathan Taverne, Armando Faz-Hernández, Diego F. Aranha, Francisco Rodríguez-Henríquez, Darrel Hankerson, Julio López
      Pages 108-123

    2. High-Speed High-Security Signatures

      • Daniel J. Bernstein, Niels Duif, Tanja Lange, Peter Schwabe, Bo-Yin Yang
      Pages 124-142

    3. To Infinity and Beyond: Combined Attack on ECC Using Points of Low Order

      • Junfeng Fan, Benedikt Gierlichs, Frederik Vercauteren
      Pages 143-159

  5. Lattices

    1. Random Sampling for Short Lattice Vectors on Graphics Cards

      • Michael Schneider, Norman Göttert
      Pages 160-175

    2. Extreme Enumeration on GPU and in Clouds

      • Po-Chun Kuo, Michael Schneider, Özgür Dagdelen, Jan Reichelt, Johannes Buchmann, Chen-Mou Cheng et al.
      Pages 176-191

    3. Modulus Fault Attacks against RSA-CRT Signatures

      • Éric Brier, David Naccache, Phong Q. Nguyen, Mehdi Tibouchi
      Pages 192-206

  6. Side Channel Attacks

    1. Breaking Mifare DESFire MF3ICD40: Power Analysis and Templates in the Real World

      • David Oswald, Christof Paar
      Pages 207-222

    2. Information Theoretic and Security Analysis of a 65-Nanometer DDSLL AES S-Box

      • Mathieu Renauld, Dina Kamel, François-Xavier Standaert, Denis Flandre
      Pages 223-239

    3. Thwarting Higher-Order Side Channel Analysis with Additive and Multiplicative Maskings

      • Laurie Genelle, Emmanuel Prouff, Michaël Quisquater
      Pages 240-255

    4. Extractors against Side-Channel Attacks: Weak or Strong?

      • Marcel Medwed, François-Xavier Standaert
      Pages 256-272

  8. Fault Attacks

    1. Meet-in-the-Middle and Impossible Differential Fault Analysis on AES

      • Patrick Derbez, Pierre-Alain Fouque, Delphine Leresteux
      Pages 274-291
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About this book

This book constitutes the proceedings of the 13th International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2011, held in Nara, Japan, from September 28 until October 1, 2011. The 32 papers presented together with 1 invited talk were carefully reviewed and selected from 119 submissions. The papers are organized in topical sections named: FPGA implementation; AES; elliptic curve cryptosystems; lattices; side channel attacks; fault attacks; lightweight symmetric algorithms, PUFs; public-key cryptosystems; and hash functions.

Editors and Affiliations

  • Department of Electrical Engineering - COSIC, Katholieke Universiteit Leuven and IBBT, Leuven-Heverlee, Belgium

    Bart Preneel

  • Institute of Mathematics for Industry, Kyushu University, Fukuoka, Japan

    Tsuyoshi Takagi

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