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Euro-Par 2010, Parallel Processing Workshops

HeteroPAR, HPCC, HiBB, CoreGrid, UCHPC, HPCF, PROPER, CCPI, VHPC, Iscia, Italy, August 31 - September 3, 2010, Revised Selected Papers

  • Conference proceedings
  • © 2011

Overview

Editors:
  1. Mario R. Guarracino

    1. CNR, ICAR, Napoli, Italy

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  2. Frédéric Vivien

    1. INRIA,  PIP ENS Lyon, Lyon, France

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  3. Jesper Larsson Träff

    1. Scientific Computing, University of Vienna, Vienna, Austria

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  4. Mario Cannatoro

    1. University of Catanzaro, Catanzaro, Italy

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  5. Marco Danelutto

    1. Dept. of Computer Science, University of Pisa, Pisa, Italy

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  6. Anders Hast

    1. Gavle Creative Media Lab, Gavle, Sweden

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  7. Francesca Perla

    1. Dept. Math & Stat, University of Naples Parthenope, Napoli, Italy

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  8. Andreas Knüpfer

    1. TU Dresden, Dresden, Germany

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  9. Beniamino Martino

    1. Dipartimento di Ingegneria dell’ Informazione, Seconda Università di Napoli, Aversa, Italy

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  10. Michael Alexander

    1. Scaledinfra technologies GmbH, Vienna, Austria

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 6586)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

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Conference proceedings info: Euro-Par 2010.

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Table of contents (85 papers)

  1. Front Matter

    Download chapter PDF

  2. Eighth International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar’2010)

    1. Front Matter

      Pages 1-1
      Download chapter PDF

    2. HeteroPar’2010: Eighth International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms

      • Frédéric Vivien
      Pages 3-3

    3. Accurate Emulation of CPU Performance

      • Tomasz Buchert, Lucas Nussbaum, Jens Gustedt
      Pages 5-12

    4. Case Studies in Automatic GPGPU Code Generation with llc

      • Ruymán Reyes, Francisco de Sande
      Pages 13-22

    5. On the Evaluation of JavaSymphony for Heterogeneous Multi-core Clusters

      • Muhammad Aleem, Radu Prodan, Thomas Fahringer
      Pages 23-30

    6. MAHEVE: An Efficient Reliable Mapping of Asynchronous Iterative Applications on Volatile and Heterogeneous Environments

      • Raphaël Couturier, David Laiymani, Sébastien Miquée
      Pages 31-39

    7. Dynamic Load Balancing of Parallel Computational Iterative Routines on Platforms with Memory Heterogeneity

      • David Clarke, Alexey Lastovetsky, Vladimir Rychkov
      Pages 41-50

    8. Dealing with Heterogeneity for Mapping MMOFPS in Distributed Systems

      • Ignasi Barri, Josep Rius, Concepció Roig, Francesc Giné
      Pages 51-61

    9. Max-Plus Algebra and Discrete Event Simulation on Parallel Hierarchical Heterogeneous Platforms

      • Brett A. Becker, Alexey Lastovetsky
      Pages 63-70

  3. Forth Workshop on Highly Parallel Processing on a Chip (HPPC 2010)

    1. Front Matter

      Pages 71-71
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    2. HPPC 2010: Forth Workshop on Highly Parallel Processing on a Chip

      • Martti Forsell, Jesper Larsson Träff
      Pages 73-75

    3. The Massively Parallel Computing Model GCA

      • Rolf Hoffmann
      Pages 77-84

    4. “Single-chip Cloud Computer”, an IA Tera-scale Research Processor

      • Jim Held
      Pages 85-85

    5. Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs

      • Alberto Ros, Manuel E. Acacio
      Pages 87-97

    6. A Work Stealing Scheduler for Parallel Loops on Shared Cache Multicores

      • Marc Tchiboukdjian, Vincent Danjean, Thierry Gautier, Fabien Le Mentec, Bruno Raffin
      Pages 99-107

    7. Resource-Agnostic Programming for Many-Core Microgrids

      • Thomas A. M. Bernard, Clemens Grelck, Michael A. Hicks, Chris R. Jesshope, Raphael Poss
      Pages 109-116

    8. Programming Heterogeneous Multicore Systems Using Threading Building Blocks

      • George Russell, Paul Keir, Alastair F. Donaldson, Uwe Dolinsky, Andrew Richards, Colin Riley
      Pages 117-125

    9. Fine-Grained Parallelization of a Vlasov-Poisson Application on GPU

      • Guillaume Latu
      Pages 127-135

    10. Highly Parallel Implementation of Harris Corner Detector on CSX SIMD Architecture

      • Fouzhan Hosseini, Amir Fijany, Jean-Guy Fontaine
      Pages 137-144
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Other volumes

  1. Euro-Par 2010 - Parallel Processing

  2. Euro-Par 2010 - Parallel Processing

  3. Euro-Par 2010 Parallel Processing Workshops

Keywords

About this book

This book constitutes thoroughly refereed post-conference proceedings of the workshops of the 16th International Conference on Parallel Computing, Euro-Par 2010, held in Ischia, Italy, in August/September 2010. The papers of these 9 workshops HeteroPar, HPCC, HiBB, CoreGrid, UCHPC, HPCF, PROPER, CCPI, and VHPC focus on promotion and advancement of all aspects of parallel and distributed computing.

Editors and Affiliations

  • CNR, ICAR, Napoli, Italy

    Mario R. Guarracino

  • INRIA,  PIP ENS Lyon, Lyon, France

    Frédéric Vivien

  • Scientific Computing, University of Vienna, Vienna, Austria

    Jesper Larsson Träff

  • University of Catanzaro, Catanzaro, Italy

    Mario Cannatoro

  • Dept. of Computer Science, University of Pisa, Pisa, Italy

    Marco Danelutto

  • Gavle Creative Media Lab, Gavle, Sweden

    Anders Hast

  • Dept. Math & Stat, University of Naples Parthenope, Napoli, Italy

    Francesca Perla

  • TU Dresden, Dresden, Germany

    Andreas Knüpfer

  • Dipartimento di Ingegneria dell’ Informazione, Seconda Università di Napoli, Aversa, Italy

    Beniamino Martino

  • Scaledinfra technologies GmbH, Vienna, Austria

    Michael Alexander

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