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Theoretical Computer Science and General Issues

High Performance Embedded Architectures and Compilers

Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings

Editors: Stenström, P., Dubois, M., Katevenis, M., Gupta, R., Ungerer, T. (Eds.)

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Table of contents (26 chapters)

Table of contents (26 chapters)
  • Supercomputing for the Future, Supercomputing from the Past (Keynote)

    Pages 3-5

    Valero, Mateo (et al.)

  • MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing

    Pages 9-21

    Kissell, Kevin D.

  • rMPI: Message Passing on Multicore Processors with On-Chip Interconnect

    Pages 22-37

    Psota, James (et al.)

  • Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE

    Pages 38-52

    Blagojevic, Filip (et al.)

  • BRAM-LUT Tradeoff on a Polymorphic DES Design

    Pages 55-65

    Chaves, Ricardo (et al.)

Buy this book

eBook $89.00
price for USA in USD (gross)
  • ISBN 978-3-540-77560-7
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Softcover $119.00
price for USA in USD
  • ISBN 978-3-540-77559-1
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
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Bibliographic Information

Bibliographic Information
Book Title
High Performance Embedded Architectures and Compilers
Book Subtitle
Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings
Editors
  • Per Stenström
  • Michel Dubois
  • Manolis Katevenis
  • Rajiv Gupta
  • Theo Ungerer
Series Title
Theoretical Computer Science and General Issues
Series Volume
4917
Copyright
2008
Publisher
Springer-Verlag Berlin Heidelberg
Copyright Holder
Springer-Verlag Berlin Heidelberg
eBook ISBN
978-3-540-77560-7
DOI
10.1007/978-3-540-77560-7
Softcover ISBN
978-3-540-77559-1
Edition Number
1
Number of Pages
XIII, 400
Topics