Theoretical Computer Science and General Issues

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings

Editors: Azemard, Nadine, Svensson, Lars (Eds.)

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  • Features the refereed proceedings of the 17th International Workshop on Power and Timing Modeling, Optimization and Simulation
  • Includes 36 full papers and 19 poster papers, along with 3 key notes and 2 industrial papers
  • Covers high level design, low power design techniques, low power analog circuits, statistical static timing analysis, power modeling and optimization, and more
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  • ISBN 978-3-540-74442-9
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About this book

th Welcome to the proceedings of PATMOS 2007, the 17 in a series of international workshops. PATMOS 2007 was organized by Chalmers University of Technology with IEEE Sweden Chapter of the Solid-State Circuit Society technical - sponsorship and IEEE CEDA sponsorship. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2007 consisted of state-of-the-art te- nical contributions, three invited talks and an industrial session on design challenges in real-life projects. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on m- eling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert - viewers, selected the 55 papers presented at PATMOS. The papers were organized into 9 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript.

Table of contents (60 chapters)

Table of contents (60 chapters)
  • System-Level Application-Specific NoC Design for Network and Multimedia Applications

    Pages 1-9

    Papadopoulos, Lazaros (et al.)

  • Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements

    Pages 10-19

    Fournel, Nicolas (et al.)

  • A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms

    Pages 20-30

    Panagopoulos, Ioannis (et al.)

  • An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture

    Pages 31-42

    Delorme, Julien

  • Template Vertical Dictionary-Based Program Compression Scheme on the TTA

    Pages 43-52

    Mingche, Lai (et al.)

Buy this book

eBook $89.00
price for USA in USD
  • ISBN 978-3-540-74442-9
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Softcover $119.99
price for USA in USD
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Bibliographic Information

Bibliographic Information
Book Title
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Book Subtitle
17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings
Editors
  • Nadine Azemard
  • Lars Svensson
Series Title
Theoretical Computer Science and General Issues
Series Volume
4644
Copyright
2007
Publisher
Springer-Verlag Berlin Heidelberg
Copyright Holder
Springer-Verlag Berlin Heidelberg
eBook ISBN
978-3-540-74442-9
DOI
10.1007/978-3-540-74442-9
Softcover ISBN
978-3-540-74441-2
Edition Number
1
Number of Pages
XIV, 586
Topics