Embedded Computer Systems: Architectures, Modeling, and Simulation

1. Front Matter

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2. Beachnote

   1. Can They Be Fixed: Some Thoughts After 40 Years in the Business

      • Yale Patt

      Pages 1-1

3. Architecture

   1. On the Benefit of Caching Traffic Flow Data in the Link Buffer

      • Konstantin Septinus, Christian Grimm, Vladislav Rumyantsev, Peter Pirsch

      Pages 2-11

   2. Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor

      • Emre Özer, Ronald G. Dreslinski, Trevor Mudge, Stuart Biles, Krisztián Flautner

      Pages 12-22

   3. Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic

      • Vladimír Guzma, Pekka Jääskeläinen, Pertti Kellomäki, Jarmo Takala

      Pages 23-32

   4. Scalable Architecture for Prefix Preserving Anonymization of IP Addresses

      • Anthony Blake, Richard Nelson

      Pages 33-42

4. New Frontiers

   1. Arithmetic Design on Quantum-Dot Cellular Automata Nanotechnology

      • Ismo Hänninen, Jarmo Takala

      Pages 43-52

   2. Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications

      • Sebastian Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramirez, Mateo Valero

      Pages 53-64

   3. 802.15.3 Transmitter: A Fast Design Cycle Using OFDM Framework in Bluespec

      • Teemu Pitkänen, Vesa-Matti Hartikainen, Nirav Dave, Gopal Raghavan

      Pages 65-74

5. SoC

   1. A Real-Time Programming Model for Heterogeneous MPSoCs

      • Torsten Limberg, Bastian Ristau, Gerhard Fettweis

      Pages 75-84

   2. A Multi-objective and Hierarchical Exploration Tool for SoC Performance Estimation

      • Alexis Vander Biest, Alienor Richard, Dragomir Milojevic, Frederic Robert

      Pages 85-95

   3. A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs

      • Francesca Palumbo, Simone Secchi, Danilo Pani, Luigi Raffo

      Pages 96-105

   4. Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors

      • Xu Guo, Zhimin Chen, Patrick Schaumont

      Pages 106-115

6. Application Specific

   1. Area Reliability Trade-Off in Improved Reed Muller Coding

      • Costas Argyrides, Stephania Loizidou, Dhiraj K. Pradhan

      Pages 116-125

   2. Efficient Reed-Solomon Iterative Decoder Using Galois Field Instruction Set

      • Daniel Iancu, Mayan Moudgill, John Glossner, Jarmo Takala

      Pages 126-135

   3. ASIP-eFPGA Architecture for Multioperable GNSS Receivers

      • Thorsten von Sydow, Holger Blume, Götz Kappen, Tobias G. Noll

      Pages 136-145

7. Special Session: System Level Design for Heterogeneous Systems

   1. Introduction to System Level Design for Heterogeneous Systems

      • John McAllister

      Pages 146-146

   2. Streaming Systems in FPGAs

      • Stephen Neuendorffer, Kees Vissers

      Pages 147-156

   3. Heterogeneous Design in Functional DIF

      • William Plishker, Nimish Sane, Mary Kiemb, Shuvra S. Bhattacharyya

      Pages 157-166

   4. Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study

      • Andy D. Pimentel, Todor Stefanov, Hristo Nikolov, Mark Thompson, Simon Polstra, Ed F. Deprettere

      Pages 167-176

This book constitutes the refereed proceedings of the 8th International Workshop on Systems, Architectures, Modeling, and Simulation, SAMOS 2008, held in Samos, Greece, in July 2008. The 24 revised full papers presented together with a contamplative keynote and additional papers of two special workshop sessions were carefully reviewed and selected from 62 submissions. The papers are organized in topical sections on architecture, new frontiers, SoC, application specific contributions, system level design for heterogeneous systems, programming multicores, sensors and sensor networks; and systems modeling and design.

• GPS
• bioinformatics
• computer
• computer architecture
• computer networking
• embedded systems
• energy efficiency
• evolutionary optimization
• flash memory
• hardware design
• modeling
• mul
• multi-core architectures
• multidimensional dataflow
• system

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