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Lecture Notes in Computer Science
cover

Correct Hardware Design and Verification Methods

10th IFIP WG10.5 Advanced Research Working Conference, CHARME'99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings

Editors: Pierre, Laurence, Kropf, Thomas (Eds.)

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About this book

CHARME’99 is the tenth in a series of working conferences devoted to the dev- opment and use of leading-edge formal techniques and tools for the design and veri?cation of hardware and systems. Previous conferences have been held in Darmstadt (1984), Edinburgh (1985), Grenoble (1986), Glasgow (1988), Leuven (1989), Torino (1991), Arles (1993), Frankfurt (1995) and Montreal (1997). This workshop and conference series has been organized in cooperation with IFIP WG 10. 5. It is now the biannual counterpart of FMCAD, which takes place every even-numbered year in the USA. The 1999 event took place in Bad Her- nalb, a resort village located in the Black Forest close to the city of Karlsruhe. The validation of functional and timing behavior is a major bottleneck in current VLSI design systems. A predominantly academic area of study until a few years ago, formal design and veri?cation techniques are now migrating into industrial use. The aim of CHARME’99 is to bring together researchers and users from academia and industry working in this active area of research. Two invited talks illustrate major current trends: the presentation by G´erard Berry (Ecole des Mines de Paris, Sophia-Antipolis, France) is concerned with the use of synchronous languages in circuit design, and the talk given by Peter Jansen (BMW, Munich, Germany) demonstrates an application of formal methods in an industrial environment. The program also includes 20 regular presentations and 12 short presentations/poster exhibitions that have been selected from the 48 submitted papers.

Table of contents (34 chapters)

Table of contents (34 chapters)
  • Esterel and Jazz : Two Synchronous Languages for Circuit Design

    Pages 1-1

    Berry, Gérard

  • Design Process of Embedded Automotive Systems—Using Model Checking for Correct Specifications

    Pages 2-7

    Jansen, Peter

  • A Proof of Correctness of a Processor Implementing Tomasulo’s Algorithm without a Reorder Buffer

    Pages 8-22

    Hosabettu, Ravi (et al.)

  • Formal Verification of Explicitly Parallel Microprocessors

    Pages 23-36

    Cook, Byron (et al.)

  • Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic

    Pages 37-53

    Velev, Miroslav N. (et al.)

Buy this book

eBook $84.99
price for USA in USD (gross)
  • ISBN 978-3-540-48153-9
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Softcover $109.00
price for USA in USD
  • ISBN 978-3-540-66559-5
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
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Bibliographic Information

Bibliographic Information
Book Title
Correct Hardware Design and Verification Methods
Book Subtitle
10th IFIP WG10.5 Advanced Research Working Conference, CHARME'99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings
Editors
  • Laurence Pierre
  • Thomas Kropf
Series Title
Lecture Notes in Computer Science
Series Volume
1703
Copyright
1999
Publisher
Springer-Verlag Berlin Heidelberg
Copyright Holder
Springer-Verlag Berlin Heidelberg
eBook ISBN
978-3-540-48153-9
DOI
10.1007/3-540-48153-2
Softcover ISBN
978-3-540-66559-5
Series ISSN
0302-9743
Edition Number
1
Number of Pages
XII, 376
Topics