Processor Architecture

1. Front Matter

   Pages I-XXII

   PDF

2. Basic Pipelining and Simple RISC Processors

   • Jurij Šilc, Borut Robič, Theo Ungerer

   Pages 1-54

3. Dataflow Processors

   • Jurij Šilc, Borut Robič, Theo Ungerer

   Pages 55-97

4. CISC Processors

   • Jurij Šilc, Borut Robič, Theo Ungerer

   Pages 99-122

5. Multiple-Issue Processors

   • Jurij Šilc, Borut Robič, Theo Ungerer

   Pages 123-219

6. Future Processors to use Fine-Grain Parallelism

   • Jurij Šilc, Borut Robič, Theo Ungerer

   Pages 221-245

7. Future Processors to use Coarse-Grain Parallelism

   • Jurij Šilc, Borut Robič, Theo Ungerer

   Pages 247-298

8. Processor-in-Memory, Reconfigurable, and Asynchronous Processors

   • Jurij Šilc, Borut Robič, Theo Ungerer

   Pages 299-333

9. Back Matter

   Pages 335-391

   PDF

Today's microprocessors are the powerful descendants of the von Neumann 1 computer dating back to a memo of Burks, Goldstine, and von Neumann of 1946. The so-called von Neumann architecture is characterized by a se­ quential control flow resulting in a sequential instruction stream. A program counter addresses the next instruction if the preceding instruction is not a control instruction such as, e. g. , jump, branch, subprogram call or return. An instruction is coded in an instruction format of fixed or variable length, where the opcode is followed by one or more operands that can be data, addresses of data, or the address of an instruction in the case of a control instruction. The opcode defines the types of operands. Code and data are stored in a common storage that is linear, addressed in units of memory words (bytes, words, etc. ). The overwhelming design criterion of the von Neumann computer was the minimization of hardware and especially of storage. The most simple implementation of a von Neumann computer is characterized by a microar­ chitecture that defines a closely coupled control and arithmetic logic unit (ALU), a storage unit, and an I/O unit, all connected by a single connection unit. The instruction fetch by the control unit alternates with operand fetches and result stores for the AL U.

• Control Speculation
• EPIC
• Mikroprozessoren
• Paralleles Rechnen
• Processor architecture
• Prozessor-Architektur
• Scheduling
• Verteilte Systeme
• computer organization
• microprocessors
• parallel processing
• processor

• Computer Systems Department, Jožef Stefan Institute, Ljubljana, Slovenia

  Jurij Šilc

• Faculty of Computer and Information Science, University of Ljubljana, Ljubljana, Slovenia

  Borut Robič

• Department of Computer Design and Fault Tolerance, University of Karsruhe, Karlsruhe, Germany

  Theo Ungerer

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