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Field-Programmable Logic and Applications

11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 Proceedings

  • Conference proceedings
  • © 2001

Overview

Editors:
  1. Gordon Brebner

    1. Division of Informatics, University of Edinburgh, Edinburgh, UK

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  2. Roger Woods

    1. School of Electrical and Electronic Engineering, Queen’s University of Belfast, Belfast, UK

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    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 2147)

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Table of contents (74 papers)

  1. Front Matter

    Pages I-XV
    Download chapter PDF

  2. Invited Keynote 1

    1. Technology Trends and Adaptive Computing

      • Michael J. Flynn, Albert A. Liddicoat
      Pages 1-5

  3. Architectural Frameworks

    1. Prototyping Framework for Reconfigurable Processors

      • Sergej Sawitzki, Steffen Köhler, Rainer G. Spallek
      Pages 6-16

    2. An Emulator for Exploring RaPiD Configurable Computing Architectures

      • Chris Fisher, Kevin Rennie, Guanbin Xing, Stefan G. Berg, Kevin Bolding, John Naegle et al.
      Pages 17-26

  4. Place and Route 1

    1. A New Placement Method for Direct Mapping into LUT-Based FPGAs

      • Joerg Abke, Erich Barke
      Pages 27-36

    2. fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits

      • Parivallal Kannan, Shankar Balachandran, Dinesh Bhatia
      Pages 37-47

  5. Architecture

    1. Macrocell Architectures for Product Term Embedded Memory Arrays

      • Ernie Lin, Steven J. E. Wilton
      Pages 48-58

    2. Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs

      • Bryan S. Goda, Kraft Russell P., Steven R. Carlough, Thomas W. Krawczyk Jr., John F. McDonald
      Pages 59-69

    3. Memory Synthesis for FPGA-Based Reconfigurable Computers

      • Amit Kasat, Iyad Ouaiss, Ranga Vemuri
      Pages 70-80

  6. DSP 1

    1. Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic

      • Stephen J. Melnikoff, Steven F. Quigley, Martin J. Russell
      Pages 81-90

    2. Implementation of (Normalised) RLS Lattice on Virtex

      • Felix Albu, Jiri Kadlec, Chris Softley, Rudolf Matousek, Antonin Hermanek, Nick Coleman et al.
      Pages 91-100

    3. Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing

      • Abbes Amira, Ahmed Bouridane, Peter Milligan
      Pages 101-111

  7. Synthesis

    1. Static Profile-Driven Compilation for FPGAs

      • Srihari Cadambi, Seth Copen Goldstein
      Pages 112-122

    2. Synthesizing RTL Hardware from Java Byte Codes

      • Michael J. Wirthlin, Brad L. Hutchings, Carl Worth
      Pages 123-132

    3. PuMA++: From Behavioral Specification to Multi-FPGA-Prototype

      • Klaus Harbich, Erich Barke
      Pages 133-141

  9. Runtime Recon.guration 1

    1. Task-Parallel Programming of Reconfigurable Systems

      • Markus Weinhardt, Wayne Luk
      Pages 172-181

    2. Chip-Based Reconfigurable Task Management

      • Gordon Brebner, Oliver Diessel
      Pages 182-191
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Keywords

Editors and Affiliations

  • Division of Informatics, University of Edinburgh, Edinburgh, UK

    Gordon Brebner

  • School of Electrical and Electronic Engineering, Queen’s University of Belfast, Belfast, UK

    Roger Woods

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