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Theoretical Computer Science and General Issues

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings

Editors: Vounckx, Johan, Azemard, Nadine, Maurine, Philippe (Eds.)

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About this book

Welcome to the proceedings of PATMOS 2006, the 16th in a series of international workshops. PATMOS 2006 was organized by LIRMM with CAS technical - sponsorship and CEDA sponsorship. Over the years, the PATMOS workshop has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design methodologies, and tools required for the development of upcoming generations of integrated circuits and systems. The technical program of PATMOS 2006 contained state-of-the-art technical contributions, three invited talks, a special session on hearing-aid design, and an embedded tutorial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert reviewers, selected the 64 papers presented at PATMOS. The papers were organized into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript.

Table of contents (70 chapters)

Table of contents (70 chapters)
  • Design of Parallel Implementations by Means of Abstract Dynamic Critical Path Based Profiling of Complex Sequential Algorithms

    Pages 1-11

    Prihozhy, Anatoly (et al.)

  • Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism

    Pages 12-23

    Scarpazza, Daniele Paolo (et al.)

  • Handheld System Energy Reduction by OS-Driven Refresh

    Pages 24-35

    Moshnyaga, Vasily G. (et al.)

  • Delay Constrained Register Transfer Level Dynamic Power Estimation

    Pages 36-46

    Sambamurthy, Sriram (et al.)

  • Circuit Design Style for Energy Efficiency: LSDL and Compound Domino

    Pages 47-55

    Yu, Xiao Yan (et al.)

Buy this book

eBook $129.00
price for USA in USD (gross)
  • ISBN 978-3-540-39097-8
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Softcover $169.00
price for USA in USD
  • ISBN 978-3-540-39094-7
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
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Bibliographic Information

Bibliographic Information
Book Title
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Book Subtitle
16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings
Editors
  • Johan Vounckx
  • Nadine Azemard
  • Philippe Maurine
Series Title
Theoretical Computer Science and General Issues
Series Volume
4148
Copyright
2006
Publisher
Springer-Verlag Berlin Heidelberg
Copyright Holder
Springer-Verlag Berlin Heidelberg
eBook ISBN
978-3-540-39097-8
DOI
10.1007/11847083
Softcover ISBN
978-3-540-39094-7
Edition Number
1
Number of Pages
XVI, 677
Topics