Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

1. Front Matter

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2. Session 1 – High-Level Design

   1. Design of Parallel Implementations by Means of Abstract Dynamic Critical Path Based Profiling of Complex Sequential Algorithms

      • Anatoly Prihozhy, Daniel Mlynek

      Pages 1-11

   2. Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism

      • Daniele Paolo Scarpazza, Praveen Raghavan, David Novo, Francky Catthoor, Diederik Verkest

      Pages 12-23

   3. Handheld System Energy Reduction by OS-Driven Refresh

      • Vasily G. Moshnyaga, Hoa Vo, Glenn Reinman, Miodrag Potkonjak

      Pages 24-35

3. Session 2 – Power Estimation / Modeling

   1. Delay Constrained Register Transfer Level Dynamic Power Estimation

      • Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri

      Pages 36-46

   2. Circuit Design Style for Energy Efficiency: LSDL and Compound Domino

      • Xiao Yan Yu, Robert Montoye, Kevin Nowka, Bart Zeydel, Vojin Oklobdzija

      Pages 47-55

   3. Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage

      • Domenik Helms, Marko Hoyer, Wolfgang Nebel

      Pages 56-65

   4. Leakage Power Characterization Considering Process Variations

      • Jose L. Rosselló, Carol de Benito, Sebastià Bota, Jaume Segura

      Pages 66-74

4. Session 3 – Memory and Register Files

   1. Heuristic for Two-Level Cache Hierarchy Exploration Considering Energy Consumption and Performance

      • A. G. Silva-Filho, F. R. Cordeiro, R. E. Sant’Anna, M. E. Lima

      Pages 75-83

   2. System Level Multi-bank Main Memory Configuration for Energy Reduction

      • Hanene Ben Fradj, Cécile Belleudy, Michel Auguin

      Pages 84-94

   3. SRAM CP: A Charge Recycling Design Schema for SRAM

      • Ka-Ming Keung, Akhilesh Tyagi

      Pages 95-106

   4. Compiler-Driven Leakage Energy Reduction in Banked Register Files

      • David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest et al.

      Pages 107-116

5. Session 4 – Low-Power Digital Circuits

   1. Impact of Array Data Flow Analysis on the Design of Energy-Efficient Circuits

      • M. Hillers, W. Nebel

      Pages 117-126

   2. Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations

      • Bart R. Zeydel, Vojin G. Oklobdzija

      Pages 127-136

   3. Low-Power Adaptive Bias Amplifier for a Large Supply-Range Linear Voltage Regulator

      • Stefan Cserveny

      Pages 137-147

   4. Circuit Sizing and Supply-Voltage Selection for Low-Power Digital Circuit Design

      • Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija

      Pages 148-156

6. Session 5 – Busses and Interconnects

   1. Power Modeling of a NoC Based Design for High Speed Telecommunication Systems

      • Philippe Grosse, Yves Durand, Paul Feautrier

      Pages 157-168

   2. Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance

      • T. Murgan, P. B. Bacinschi, A. García Ortiz, M. Glesner

      Pages 169-180

   3. Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology

      • Kenichi Okada, Takumi Uezono, Kazuya Masu

      Pages 181-190

   4. Two Efficient Synchronous \(\Leftrightarrow\) Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures

      • A. Sheibanyrad, A. Greiner

      Pages 191-202

Welcome to the proceedings of PATMOS 2006, the 16th in a series of international workshops. PATMOS 2006 was organized by LIRMM with CAS technical - sponsorship and CEDA sponsorship. Over the years, the PATMOS workshop has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design methodologies, and tools required for the development of upcoming generations of integrated circuits and systems. The technical program of PATMOS 2006 contained state-of-the-art technical contributions, three invited talks, a special session on hearing-aid design, and an embedded tutorial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert reviewers, selected the 64 papers presented at PATMOS. The papers were organized into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript.

• DOM
• calculus
• circuit design
• configuration
• electromagnetic compatibility
• field-effect transistor
• integrated circuit
• integrated circuits
• low power desing
• metal oxide semiconductur field-effect transistor
• optimization
• performance evaluation
• power consumption
• processor architecture
• systems design

• IMEC, Heverlee, Belgium

  Johan Vounckx

• LIRMM, UMR CNRS/Université de Montpellier II, (C5506), Montpellier, France

  Nadine Azemard

• University of Montpellier / LIRMM, II, Montpellier, France

  Philippe Maurine

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