Authors:
- Provides readers with a single-source guide to the entire domain of functional design verification
- Describe many industry standard tools available in the market so readers know which tools to pursue to their greatest advantage
- Includes complete working Verification Plans of complex SoCs and numerous, real applications to demonstrate each topic introduced
- Written to be highly accessible and easy to digest
- Includes supplementary material: sn.pub/extras
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Table of contents (18 chapters)
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Front Matter
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Back Matter
About this book
Authors and Affiliations
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Los Gatos, USA
Ashok B. Mehta
About the author
Ashok Mehta has been working in the ASIC/SoC design and verification field for over 20 years. He started his career at Digital Equipment Corporation (DEC) working as a CPU design engineer. He then worked at Data General, Intel (first Pentium Architecture Verification team) and after a route of couple of startups, worked at Applied Micro and currently at TSMC.
He was a very early adopter of Verilog and participated in Verilog, VHDL, iHDL (Intel HDL) and SDF (standard delay format) technical subcommittees. He has also been a proponent of ESL (Electronic System Level) designs. At TSMC he architected and went into production with two industry standard TSMC ESL Reference Flows that take designs from ESL to RTL while preserving the verification environment for reuse from ESL to RTL.
He holds 14 U.S. Patents in the field of SoC and 3DIC design verification.
He is also the author of Second Edition of the book “SystemVerilog Assertions and FunctionalCoverage – A comprehensive guide to languages, methodologies and applications”. Springer (June 2016).
Ashok earned an MSEE from University of Missouri.
In his spare time, he is an amateur photographer and likes to play drums on 70’s rock music driving his neighbors up the wall J
Bibliographic Information
Book Title: ASIC/SoC Functional Design Verification
Book Subtitle: A Comprehensive Guide to Technologies and Methodologies
Authors: Ashok B. Mehta
DOI: https://doi.org/10.1007/978-3-319-59418-7
Publisher: Springer Cham
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer International Publishing AG 2018
Hardcover ISBN: 978-3-319-59417-0Published: 07 July 2017
Softcover ISBN: 978-3-319-86620-8Published: 12 August 2018
eBook ISBN: 978-3-319-59418-7Published: 28 June 2017
Edition Number: 1
Number of Pages: XXXI, 328
Number of Illustrations: 15 b/w illustrations, 160 illustrations in colour
Topics: Circuits and Systems, Processor Architectures, Logic Design