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Wafer-Level Chip-Scale Packaging

Analog and Power Semiconductor Applications

Authors: Qu, Shichun, Liu, Yong

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  • Covers the development of wafer level power discrete packaging with regular wafer level design concept and directly bumping technology
  • Introduces the development of the analog and power SIP/3D/TSV/stack die packaging technology
  • Presents the wafer level analog IC packaging design through fan-in and fan-out with RDLs
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eBook $89.00
price for USA in USD
  • ISBN 978-1-4939-1556-9
  • Digitally watermarked, DRM-free
  • Included format: EPUB, PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $169.99
price for USA in USD
Softcover $119.99
price for USA in USD
About this book

Analog and Power Wafer Level Chip Scale Packaging presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Since the analog and power electronic wafer level packaging is different from regular digital and memory IC package, this book will systematically introduce the typical analog and power electronic wafer level packaging design, assembly process, materials, reliability and failure analysis, and material selection. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical and stress modeling methodologies is also presented in the book.

Reviews

“Wafer Level Chip-Scale Packaging by Qu, Shichun, Liu, Yong presents good technical insights of wafer-level chip scale packaging (WLCSP) technology, suitable for both industry and academic practitioners. … It is a good reference to demonstrate the alternate wafer-level chip scale packaging, and can serve as a very informative technical reference. … The book is valuable as a learning tool for WLCSP and its clear relevance to real-world industry practices make it useful for both students and reliability practitioners.” (Chong Leong Gan and Uda Hashim, Microelectronics Reliability, August, 2015)


Table of contents (10 chapters)

Table of contents (10 chapters)

Buy this book

eBook $89.00
price for USA in USD
  • ISBN 978-1-4939-1556-9
  • Digitally watermarked, DRM-free
  • Included format: EPUB, PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $169.99
price for USA in USD
Softcover $119.99
price for USA in USD
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Bibliographic Information

Bibliographic Information
Book Title
Wafer-Level Chip-Scale Packaging
Book Subtitle
Analog and Power Semiconductor Applications
Authors
Copyright
2015
Publisher
Springer-Verlag New York
Copyright Holder
Springer Science+Business Media New York
eBook ISBN
978-1-4939-1556-9
DOI
10.1007/978-1-4939-1556-9
Hardcover ISBN
978-1-4939-1555-2
Softcover ISBN
978-1-4939-5438-4
Edition Number
1
Number of Pages
XVII, 322
Number of Illustrations
58 b/w illustrations, 256 illustrations in colour
Topics