Routing Algorithms in Networks-on-Chip
Editors: Palesi, Maurizio, Daneshtalab, Masoud (Eds.)
- Provides a comprehensive overview of routing algorithms for Networks-on-Chip and NoC-based, manycore systems
- Describes routing algorithms for NoC architectures at all abstraction levels, from the algorithmic level to actual implementation
- Discusses the impact on NoC routing algorithms of key design objectives, such as power dissipation, energy consumption, thermal aspects, reliability, and performance
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- About this book
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This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation. Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability.
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Bibliographic Information
- Bibliographic Information
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- Book Title
- Routing Algorithms in Networks-on-Chip
- Editors
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- Maurizio Palesi
- Masoud Daneshtalab
- Copyright
- 2014
- Publisher
- Springer-Verlag New York
- Copyright Holder
- Springer Science+Business Media New York
- eBook ISBN
- 978-1-4614-8274-1
- DOI
- 10.1007/978-1-4614-8274-1
- Hardcover ISBN
- 978-1-4614-8273-4
- Softcover ISBN
- 978-1-4939-5511-4
- Edition Number
- 1
- Number of Pages
- XIV, 410
- Number of Illustrations
- 122 b/w illustrations, 97 illustrations in colour
- Topics
