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Extreme Statistics in Nanoscale Memory Design

  • Book
  • © 2010

Overview

Editors:
  1. Amith Singhee

    1. T.J. Watson Research Center, IBM Corporation, Yorktown Heights, USA

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  2. Rob A. Rutenbar

    1. Department of Computer Science, University of Illinois at Urbana-Champai, Urbana, USA

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    You can also search for this editor in PubMed   Google Scholar

  • Includes a treatment of memory design from the perspective of statistical analysis
  • Covers relevant theoretical background from other fields: statistics, machine learning, optimization, reliability
  • Explains the problem of estimating statistics of memory performance variation
  • Shows solutions recently proposed in the Electronic Design Automation (EDA) community
  • Contains chapters contributed from both industry and academia
  • Includes supplementary material: sn.pub/extras

Part of the book series: Integrated Circuits and Systems (ICIR)

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Table of contents (8 chapters)

  1. Front Matter

    Pages i-ix
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  2. Introduction

    • Amith Singhee
    Pages 1-8

  3. Extreme Statistics in Memories

    • Amith Singhee
    Pages 9-15

  4. Statistical Nano CMOS Variability and Its Impact on SRAM

    • Asen Asenov
    Pages 17-49

  5. Importance Sampling-Based Estimation: Applications to Memory Design

    • Rouwaida Kanj, Rajiv Joshi
    Pages 51-96

  6. Direct SRAM Operation Margin Computation with Random Skews of Device Characteristics

    • Robert C. Wong
    Pages 97-136

  7. Yield Estimation by Computing Probabilistic Hypervolumes

    • Chenjie Gu, Jaijeet Roychowdhury
    Pages 137-177

  8. Most Probable Point-Based Methods

    • Xiaoping Du, Wei Chen, Yu Wang
    Pages 179-202

  9. Extreme Value Theory: Application to Memory Statistics

    • Robert C. Aitken, Amith Singhee, Rob A. Rutenbar
    Pages 203-240

  10. Back Matter

    Pages 241-246
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Keywords

About this book

Knowledge exists: you only have to ?nd it VLSI design has come to an important in?ection point with the appearance of large manufacturing variations as semiconductor technology has moved to 45 nm feature sizes and below. If we ignore the random variations in the manufacturing process, simulation-based design essentially becomes useless, since its predictions will be far from the reality of manufactured ICs. On the other hand, using design margins based on some traditional notion of worst-case scenarios can force us to sacri?ce too much in terms of power consumption or manufacturing cost, to the extent of making the design goals even infeasible. We absolutely need to explicitly account for the statistics of this random variability, to have design margins that are accurate so that we can ?nd the optimum balance between yield loss and design cost. This discontinuity in design processes has led many researchers to develop effective methods of statistical design, where the designer can simulate not just the behavior of the nominal design, but the expected statistics of the behavior in manufactured ICs. Memory circuits tend to be the hardest hit by the problem of these random variations because of their high replication count on any single chip, which demands a very high statistical quality from the product. Requirements of 5–6s (0.

Editors and Affiliations

  • T.J. Watson Research Center, IBM Corporation, Yorktown Heights, USA

    Amith Singhee

  • Department of Computer Science, University of Illinois at Urbana-Champai, Urbana, USA

    Rob A. Rutenbar

Bibliographic Information

  • Book Title: Extreme Statistics in Nanoscale Memory Design

  • Editors: Amith Singhee, Rob A. Rutenbar

  • Series Title: Integrated Circuits and Systems

  • DOI: https://doi.org/10.1007/978-1-4419-6606-3

  • Publisher: Springer New York, NY

  • eBook Packages: Engineering, Engineering (R0)

  • Copyright Information: Springer Science+Business Media, LLC 2010

  • Hardcover ISBN: 978-1-4419-6605-6Published: 17 September 2010

  • Softcover ISBN: 978-1-4614-2672-1Published: 05 November 2012

  • eBook ISBN: 978-1-4419-6606-3Published: 09 September 2010

  • Series ISSN: 1558-9412

  • Series E-ISSN: 1558-9420

  • Edition Number: 1

  • Number of Pages: X, 246

  • Topics: Circuits and Systems, Electronics and Microelectronics, Instrumentation

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