Hardware Acceleration of EDA Algorithms

1. Front Matter

   Pages i-xxii

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2. Introduction

   • Kanupriya Gulati, Sunil P. Khatri

   Pages 1-5

3. Alternative Hardware Platforms

   1. Front Matter

      Pages 7-8

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   2. Hardware Platforms

      • Kanupriya Gulati, Sunil P. Khatri

      Pages 9-22

   3. GPU Architecture and the CUDA Programming Model

      • Kanupriya Gulati, Sunil P. Khatri

      Pages 23-30

4. Control-Dominated Category

   1. Front Matter

      Pages 31-32

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5. Control Dominated Category

   1. Accelerating Boolean Satisfiability on a Custom IC

      • Kanupriya Gulati, Sunil P. Khatri

      Pages 33-61

   2. Accelerating Boolean Satisfiability on an FPGA

      • Kanupriya Gulati, Sunil P. Khatri

      Pages 63-81

   3. Accelerating Boolean Satisfiability on a Graphics Processing Unit

      • Kanupriya Gulati, Sunil P. Khatri

      Pages 83-99

6. Control Plus Data Parallel Applications

   1. Front Matter

      Pages 101-103

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   2. Accelerating statistical static Timing Analysis Using Graphics Processors

      • Kanupriya Gulati, Sunil P. Khatri

      Pages 105-118

   3. Accelerating Fault Simulation Using Graphics Processors

      • Kanupriya Gulati, Sunil P. Khatri

      Pages 119-132

   4. Fault Table Generation Using Graphics Processors

      • Kanupriya Gulati, Sunil P. Khatri

      Pages 133-152

   5. Accelerating Circuit Simulation Using Graphics Processors

      • Kanupriya Gulati, Sunil P. Khatri

      Pages 153-165

7. Automated Generation of GPU Code

   1. Front Matter

      Pages 167-167

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   2. Automated Approach for Graphics Processor Based Software Acceleration

      • Kanupriya Gulati, Sunil P. Khatri

      Pages 169-180

   3. Conclusions

      • Kanupriya Gulati, Sunil P. Khatri

      Pages 181-187

8. Back Matter

   Pages 189-192

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Single-threaded software applications have ceased to see signi?cant gains in p- formance on a general-purpose CPU, even with further scaling in very large scale integration (VLSI) technology. This is a signi?cant problem for electronic design automation (EDA) applications, since the design complexity of VLSI integrated circuits (ICs) is continuously growing. In this research monograph, we evaluate custom ICs, ?eld-programmable gate arrays (FPGAs), and graphics processors as platforms for accelerating EDA algorithms, instead of the general-purpose sing- threaded CPU. We study applications which are used in key time-consuming steps of the VLSI design ?ow. Further, these applications also have different degrees of inherent parallelism in them. We study both control-dominated EDA applications and control plus data parallel EDA applications. We accelerate these applications on these different hardware platforms. We also present an automated approach for accelerating certain uniprocessor applications on a graphics processor. This monograph compares custom ICs, FPGAs, and graphics processing units (GPUs) as potential platforms to accelerate EDA algorithms. It also provides details of the programming model used for interfacing with the GPUs.

• FPGA
• Field Programmable Gate Array
• algorithms
• architecture
• computer-aided design (CAD)
• integrated circuit
• micro-alloy transistor, MAT
• model
• simulation
• static-induction transistor

• Coppell, U.S.A.

  Kanupriya Gulati

• Dept. Electrical & Computer Engineering, Texas A & M University, College Station, U.S.A.

  Sunil P. Khatri

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