Hardware Acceleration of EDA Algorithms
Custom ICs, FPGAs and GPUs
Authors: Khatri, Sunil P, Gulati, Kanupriya
Free Preview- Provides guidelines on whether to use GPUs or FPGAs when accelerating a given EDA algorithm, with validation by a concrete example implemented on both platforms
- Demonstrates the acceleration of several popular EDA algorithms on GPUs with speedups from 30X to 800X
- Presents techniques in a way that the readers can use example algorithms presented to determine how best to accelerate their specific EDA algorithm
- Discusses an automatic approach to generate GPU code, given regular uniprocessor code
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- About this book
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Hardware Acceleration of EDA Algorithms: Custom ICs, FPGAs and GPUs
Kanupriya Gulati
Sunil P. Khatri
This book deals with the acceleration of EDA algorithms using hardware platforms such as Custom ICs, FPGAs and GPUs. Widely applied CAD algorithms are studied for potential acceleration on these platforms. Coverage includes discussion of conditions under which it is preferable to use one platform over another, e.g., when an EDA problem has a high degree of data parallelism, the GPU is typically the preferred platform, whereas when the problem has more control, an FPGA may be preferred. Results are presented for the acceleration of several CAD algorithms (fault simulation, fault table generation, model card evaluation in SPICE, Monte Carlo based statistical static timing analysis, Boolean Satisfiability), demonstrating speedups up to 800X compared to single-core implementatinos of these algorithms.This book serves as a valuable guide on how best to leverage parallelism to accelerate CAD algorithms. It also presents a methodology to automatically extract SIMD parallelism from regular uniprocessor code which satisfies a set of constraints. With this approach, such uniprocessor code can automatically be converted to GPU code, allowing for significant acceleration. This approach is particularly useful since different GPUs have vastly different specifications, making the manual generation of GPU code an unscalable proposition.
In particular, this book:
- Provides guidelines on whether to use Custom ICs, GPUs or FPGAs when accelerating a given EDA algorithm, validating these suggestions with a concrete example (Boolean Satisfiability) implemented on all these platforms;
- Demonstrates the acceleration of several popular EDA algorithms on GPUs, with speedups up to 800X;
- Helps the reader by presenting example algorithms which may be used by the reader to determine how best to accelerate their specific EDA algorithm;
- Discusses an automatic approach to generate GPU code, given regular uniprocessor code which satisfies a set of constraints;
- Serves as a valuable reference for anyone interested in exploring alternative hardware platforms for accelerating various EDA applications by harnessing the parallelism available in these platforms.
- Table of contents (12 chapters)
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Introduction
Pages 1-5
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Hardware Platforms
Pages 9-22
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GPU Architecture and the CUDA Programming Model
Pages 23-30
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Accelerating Boolean Satisfiability on a Custom IC
Pages 33-61
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Accelerating Boolean Satisfiability on an FPGA
Pages 63-81
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Table of contents (12 chapters)
- Download Preface 1 PDF (46.2 KB)
- Download Sample pages 1 PDF (273 KB)
- Download Table of contents PDF (42.9 KB)
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Bibliographic Information
- Bibliographic Information
-
- Book Title
- Hardware Acceleration of EDA Algorithms
- Book Subtitle
- Custom ICs, FPGAs and GPUs
- Authors
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- Sunil P Khatri
- Kanupriya Gulati
- Copyright
- 2010
- Publisher
- Springer US
- Copyright Holder
- Springer-Verlag US
- eBook ISBN
- 978-1-4419-0944-2
- DOI
- 10.1007/978-1-4419-0944-2
- Hardcover ISBN
- 978-1-4419-0943-5
- Softcover ISBN
- 978-1-4899-8333-6
- Edition Number
- 1
- Number of Pages
- XXII, 192
- Topics
