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Frontiers in Electronic Testing

Verification by Error Modeling

Using Testing Techniques in Hardware Verification

Authors: Radecka, Katarzyna, Zilic, Zeljko

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eBook $139.00
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  • ISBN 978-0-306-48739-2
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Hardcover $179.99
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Softcover $209.00
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  • ISBN 978-1-4419-5402-2
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About this book

1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, including a 3 MB third level cache. A billion transistor IC was said to be “imminently doable” by Intel fellow J. Crawford at Microprocessor Forum in October 2002 [40]. Obviously, designing such complex circuits poses real challenges to engineers. Certainly, no relief comes from the competitive marketplace, with increasing demands for a very narrow window of time (time-to-market) in engineering a ready product. Therefore, a systematic and well-structured approach to designing ICs is a must. Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In general, however, a typical product cycle includes few milestones. An idea for a new product starts usually from an - depth market analysis of customer needs. Once a window of opportunity is found, product requirements are carefully specified. Ideally, these parameters would not change during the design process. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design.

Reviews

From the reviews:

"This monograph presents, as its main contribution, methods to gain more confidence in verification by simulation. … The methods presented in this book may be suitable to verify gate level circuits which may have small modifications after automatic optimization or some manual interaction." (Reiner Kolla, Zentralblatt MATH, Vol. 1049 (24), 2004)


Table of contents (8 chapters)

Buy this book

eBook $139.00
price for USA in USD (gross)
  • ISBN 978-0-306-48739-2
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $179.99
price for USA in USD
  • ISBN 978-1-4020-7652-7
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $209.00
price for USA in USD
  • ISBN 978-1-4419-5402-2
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
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Bibliographic Information

Bibliographic Information
Book Title
Verification by Error Modeling
Book Subtitle
Using Testing Techniques in Hardware Verification
Authors
Series Title
Frontiers in Electronic Testing
Series Volume
25
Copyright
2003
Publisher
Springer US
Copyright Holder
Springer Science+Business Media Dordrecht
eBook ISBN
978-0-306-48739-2
DOI
10.1007/b105974
Hardcover ISBN
978-1-4020-7652-7
Softcover ISBN
978-1-4419-5402-2
Series ISSN
0929-1296
Edition Number
1
Number of Pages
XV, 216
Topics