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The Verilog® Hardware Description Language

  • Textbook
  • © 2002

Overview

Authors:
  1. Donald E. Thomas

    1. ECE Department, Carnegie Mellon University, Pittsburgh

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    You can also search for this author in PubMed   Google Scholar

  2. Philip R. Moorby

    1. Co-design Automation, Inc., USA

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Table of contents (11 chapters)

  1. Front Matter

    Pages i-xxi
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  2. Verilog — A Tutorial Introduction

    Pages 1-34

  3. Logic Synthesis

    Pages 35-71

  4. Behavioral Modeling

    Pages 73-107

  5. Concurrent Processes

    Pages 109-142

  6. Module Hierarchy

    Pages 143-155

  7. Logic Level Modeling

    Pages 157-193

  8. Cycle-Accurate Specification

    Pages 195-210

  9. Advanced Timing

    Pages 211-238

  10. User-Defined Primitives

    Pages 239-250

  11. Switch Level Modeling

    Pages 251-282

  12. Projects

    Pages 283-292

  13. Back Matter

    Pages 293-381
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Keywords

About this book

xv From the Old to the New xvii Acknowledgments xxi 1 Verilog – A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("

Authors and Affiliations

  • ECE Department, Carnegie Mellon University, Pittsburgh

    Donald E. Thomas

  • Co-design Automation, Inc., USA

    Philip R. Moorby

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