System on Chip Design Languages

1. Front Matter

   Pages i-ix

   PDF

2. HDL standardization

   1. Front Matter

      Pages 1-1

      PDF

   2. VHDL 2001: What’s New

      • J. Bhasker, Paul J. Menchini

      Pages 3-10

   3. Verilog-2001 Behavioral and Synthesis Enhancements

      • Clifford E. Cummings

      Pages 11-33

   4. Advanced ASIC Sign-Off Features of IEEE 1076.4-2000 And Standards updates to Verilog and SDF

      • Steve Wadsworth, Dennis Brophy

      Pages 35-42

3. Analog System Modeling and Design

   1. Front Matter

      Pages 43-43

      PDF

   2. VHDL-AMS Model of a Synchronous Oscillator including Phase Noise

      • A. Fakhfakh, N. Milet-Lewis, J-B. Bégueret, H. Lévi

      Pages 45-58

   3. AnalogSL

      • Ch. Grimm, P. Oehler, Ch. Meise, K. Waldschmidt, W. Frey

      Pages 59-67

   4. Modeling Micro-Mechanical Structures for System Simulations

      • Lars M. Voßkämper, Rainer Schmid, Georg Pelz

      Pages 69-78

   5. A Comparison of Mixed-Signal Modeling Approaches

      • Gregory D. Peterson

      Pages 79-86

   6. A unified IP Design Platform for extremly flexible High Performance RF and AMS Macros using Standard Design Tools

      • Reimund Wittmann, Mohsen Darianian, Dirk Bierbaum, Pasi Ruhanen, Werner Schardein

      Pages 87-97

   7. Analog Filter Synthesis from VHDL-AMS

      • Fazrena A. Hamid, Tom J. Kazmierski

      Pages 99-109

4. System Design Experiences

   1. Front Matter

      Pages 111-111

      PDF

   2. Using GNU Make to Automate the Recompile of VHDL SoC Designs

      • Michael D. McKinney

      Pages 113-127

   3. Wild Blue Yonder: Experiences in Designing an FPGA with State Machines for a Modern Fighter Jet, Using VHDL and DesignBook

      • Brian L. Snyder

      Pages 129-137

   4. Analysis of Modelling and Simulation Capabilities in SystemC and Ocapi using a Video Filter Design

      • Benny Thörnberg, Mattias O’Nils

      Pages 139-149

   5. The Guidelines and JPEG Encoder Study Case of System Level Architecture Exploration Using the SpecC Methodology

      • Lukai Cai, Mike Olivarez, Dan Gajski

      Pages 151-161

   6. Provision and Integration of EDA Web-Services Using WSDL-based Markup

      • Heinz-Josef Eikerling, Wolfgang Thronicke, Siegfried Bublitz

      Pages 163-172

5. System Verification

   1. Front Matter

      Pages 173-173

      PDF

   2. A Mixed C/Verilog Dual-Platform Simulator

      • David A. Burgoon, Edward W. Powell, John A. Sundragon Waitz

      Pages 175-186

This book is the third in a series of books collecting the best papers from the three main regional conferences on electronic system design languages, HDLCon in the United States, APCHDL in Asia-Pacific and FDL in Europe. Being APCHDL bi-annual, this book presents a selection of papers from HDLCon'Ol and FDL'OI. HDLCon is the premier HDL event in the United States. It originated in 1999 from the merging of the International Verilog Conference and the Spring VHDL User's Forum. The scope of the conference expanded from specialized languages such as VHDL and Verilog to general purpose languages such as C++ and Java. In 2001 it was held in February in Santa Clara, CA. Presentations from design engineers are technical in nature, reflecting real life experiences in using HDLs. EDA vendors presentations show what is available - and what is planned-for design tools that utilize HDLs, such as simulation and synthesis tools. The Forum on Design Languages (FDL) is the European forum to exchange experiences and learn of new trends, in the application of languages and the associated design methods and tools, to design complex electronic systems. FDL'OI was held in Lyon, France, around seven interrelated workshops, Hardware Description Languages, Analog and Mixed signal Specification, C/C++ HW/SW Specification and Design, Design Environments & Languages, Real-Time specification for embedded Systems, Architecture Modeling and Reuse and System Specification & Design Languages.

• C programming language
• C++
• Constraint
• FPGA
• General Purpose Language
• modeling
• selection
• simulation
• system on chip (SoC)
• tools

• L3i/INSA, Lyon, France

  Anne Mignotte

• University of Cantabria, Spain

  Eugenio Villar

• Accelera, USA

  Lynn Horobin

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