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Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms

Authors: Kogel, Tim, Leupers, Rainer, Meyr, Heinrich

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Softcover $159.99
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About this book

We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking geometries do not leadtoacorrespondingincreaseofperformance. InarecenttalkLisaSuofIBM pointed out that in 65nm technology only about 25% of performance increase can be attributed to scaling geometries while the lion share is due to innovative processor architecture [1]. We believe that this fact will revolutionize the entire semiconductor industry. What is the reason for the end of the traditional view of Moore’s law? It is instructive to look at the major drivers of the semiconductor industry: wireless communications and multimedia. Both areas are characterized by a rapidly increasingdemandofcomputationalpowerinordertoprocessthesophisticated algorithmsnecessarytooptimallyutilizethepreciousresourcebandwidth. The computational power cannot be provided by traditional processor architectures and shared bus type of interconnects. The simple reason for this fact is energy ef?ciency: there exist orders of magnitude between the energy ef?ciency of an algorithm implemented as a ?xed functionality computational element and of a software implementation on a processor.

Reviews

From the reviews:

"The book covers most of the major areas of system-level design and modeling, and much of the work described has been incorporated into a commercial ESL tool … . This book’s scope and range of pragmatic ideas make it valuable for a wide audience. … When combined with the extensive list of references (260!), this is a very valuable resource for anyone interested in the area … . It should resonate with students, researchers, and practical designers … ." (Grant Martin, IEEE Design and Test of Computers, May-June, 2007)


Table of contents (10 chapters)

Table of contents (10 chapters)
  • Introduction

    Pages 1-7

  • Embedded SOC applications

    Pages 9-14

  • Classification of platform elements

    Pages 15-32

  • System level design principles

    Pages 33-42

  • Related work

    Pages 43-58

Buy this book

eBook $119.00
price for USA in USD
  • ISBN 978-1-4020-4826-5
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $199.99
price for USA in USD
  • ISBN 978-1-4020-4825-8
  • Free shipping for individuals worldwide
  • Institutional customers should get in touch with their account manager
  • Covid-19 shipping restrictions
  • Usually ready to be dispatched within 3 to 5 business days, if in stock
Softcover $159.99
price for USA in USD
  • ISBN 978-90-481-7202-3
  • Free shipping for individuals worldwide
  • Institutional customers should get in touch with their account manager
  • Covid-19 shipping restrictions
  • Usually ready to be dispatched within 3 to 5 business days, if in stock
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Bibliographic Information

Bibliographic Information
Book Title
Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
Authors
Copyright
2006
Publisher
Springer Netherlands
Copyright Holder
Springer Science+Business Media B.V.
eBook ISBN
978-1-4020-4826-5
DOI
10.1007/1-4020-4826-2
Hardcover ISBN
978-1-4020-4825-8
Softcover ISBN
978-90-481-7202-3
Edition Number
1
Number of Pages
XIV, 186
Topics