Happy holidays from us to you—get up to $30 off your next print or eBook! Shop now >>

The Springer International Series in Engineering and Computer Science

Digit-Serial Computation

Authors: Hartley, Richard, Parhi, Keshab

Buy this book

eBook $189.00
price for USA in USD (gross)
  • ISBN 978-1-4615-2327-7
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $229.99
price for USA in USD
  • ISBN 978-0-7923-9573-7
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $249.99
price for USA in USD
  • ISBN 978-1-4613-5985-2
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
About this book

Digital signal processing (DSP) is used in a wide range of applications such as speech, telephone, mobile radio, video, radar and sonar. The sample rate requirements of these applications range from 10 KHz to 100 MHz. Real time implementation of these systems requires design of hardware which can process signal samples as these are received from the source, as opposed to storing them in buffers and processing them in batch mode. Efficient implementation of real­ time hardware for DSP applications requires study of families of architectures and implementation styles out of which an appropriate architecture can be selected for a specified application. To this end, the digit-serial implementation style is proposed as an appropriate design methodology for cases where bit-serial systems cannot meet the sample rate requirements, and bit-parallel systems require excessive hardware. The number of bits processed in a clock cycle is referred to as the digit-size. The hardware complexity and the achievable sample rate increase with increase in the digit-size. As special cases, a digit­ serial system is reduced to bit-serial or bit-parallel when the digit-size is selected to equal one or the word-length, respectively. A family of implementations can be obtained by changing the digit-size parameter, thus permitting an optimal trade-off between throughput and size. Because of their structured architecture, digit-serial designs lend themselves to automatic compilation from algorithmic descriptions. An implementation of this design methodology, the Parsifal silicon compiler was developed at the General Electric Corporate Research and Development laboratory.

Table of contents (13 chapters)

Buy this book

eBook $189.00
price for USA in USD (gross)
  • ISBN 978-1-4615-2327-7
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $229.99
price for USA in USD
  • ISBN 978-0-7923-9573-7
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $249.99
price for USA in USD
  • ISBN 978-1-4613-5985-2
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Loading...

Recommended for you

Loading...

Bibliographic Information

Bibliographic Information
Book Title
Digit-Serial Computation
Authors
Series Title
The Springer International Series in Engineering and Computer Science
Series Volume
316
Copyright
1995
Publisher
Springer US
Copyright Holder
Springer Science+Business Media New York
eBook ISBN
978-1-4615-2327-7
DOI
10.1007/978-1-4615-2327-7
Hardcover ISBN
978-0-7923-9573-7
Softcover ISBN
978-1-4613-5985-2
Series ISSN
0893-3405
Edition Number
1
Number of Pages
XIII, 306
Topics