The Springer International Series in Engineering and Computer Science

Hierarchical Modeling for VLSI Circuit Testing

Authors: Bhattacharya, Debashis, Hayes, John P.

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About this book

Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing probĀ­ lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.

Table of contents (5 chapters)

Table of contents (5 chapters)

Buy this book

eBook $109.00
price for USA in USD (gross)
  • ISBN 978-1-4613-1527-8
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $179.00
price for USA in USD
  • ISBN 978-0-7923-9058-9
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
Softcover $139.99
price for USA in USD
  • ISBN 978-1-4612-8819-0
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
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Bibliographic Information

Bibliographic Information
Book Title
Hierarchical Modeling for VLSI Circuit Testing
Authors
Series Title
The Springer International Series in Engineering and Computer Science
Series Volume
89
Copyright
1990
Publisher
Springer US
Copyright Holder
Kluwer Academic Publishers
eBook ISBN
978-1-4613-1527-8
DOI
10.1007/978-1-4613-1527-8
Hardcover ISBN
978-0-7923-9058-9
Softcover ISBN
978-1-4612-8819-0
Series ISSN
0893-3405
Edition Number
1
Number of Pages
XII, 160
Topics