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Loop Tiling for Parallelism

  • Book
  • © 2000

Overview

Authors:
  1. Jingling Xue

    1. School of Computer Science and Engineering, The University of New South Wales, Sydney, Australia

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Part of the book series: The Springer International Series in Engineering and Computer Science (SECS, volume 575)

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Table of contents (7 chapters)

  1. Front Matter

    Pages i-xix
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  2. Mathematic Background and Loop Transformation

    1. Front Matter

      Pages 1-1
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    2. Mathematical Background

      • Jingling Xue
      Pages 3-33

    3. Nonsingular Transformations and Permutability

      • Jingling Xue
      Pages 35-69

  3. Tiling as a Loop Transformation

    1. Front Matter

      Pages 71-71
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    2. Rectangular Tiling

      • Jingling Xue
      Pages 73-99

    3. Parallelepiped Tiling

      • Jingling Xue
      Pages 101-120

  4. Tiling for Distributed-Memory Machines

    1. Front Matter

      Pages 121-121
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    2. SPMD Code Generation

      • Jingling Xue
      Pages 123-168

    3. Communication-Minimal Tiling

      • Jingling Xue
      Pages 169-197

    4. Time-Minimal Tiling

      • Jingling Xue
      Pages 199-246

  5. Back Matter

    Pages 247-256
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Keywords

About this book

Loop tiling, as one of the most important compiler optimizations, is beneficial for both parallel machines and uniprocessors with a memory hierarchy. This book explores the use of loop tiling for reducing communication cost and improving parallelism for distributed memory machines. The author provides mathematical foundations, investigates loop permutability in the framework of nonsingular loop transformations, discusses the necessary machineries required, and presents state-of-the-art results for finding communication- and time-minimal tiling choices. Throughout the book, theorems and algorithms are illustrated with numerous examples and diagrams. The techniques presented in Loop Tiling for Parallelism can be adapted to work for a cluster of workstations, and are also directly applicable to shared-memory machines once the machines are modeled as BSP (Bulk Synchronous Parallel) machines.
Features and key topics:
  • Detailed review of the mathematical foundations, including convex polyhedra and cones;
  • Self-contained treatment of nonsingular loop transformations, code generation, and full loop permutability;
  • Tiling loop nests by rectangles and parallelepipeds, including their mathematical definition, dependence analysis, legality test, and code generation;
  • A complete suite of techniques for generating SPMD code for a tiled loop nest;
  • Up-to-date results on tile size and shape selection for reducing communication and improving parallelism;
  • End-of-chapter references for further reading.
Researchers and practitioners involved in optimizing compilers and students in advanced computer architecture studies will find this a lucid and well-presented reference work with numerous citations to original sources.

Authors and Affiliations

  • School of Computer Science and Engineering, The University of New South Wales, Sydney, Australia

    Jingling Xue

Bibliographic Information

  • Book Title: Loop Tiling for Parallelism

  • Authors: Jingling Xue

  • Series Title: The Springer International Series in Engineering and Computer Science

  • DOI: https://doi.org/10.1007/978-1-4615-4337-4

  • Publisher: Springer New York, NY

  • eBook Packages: Springer Book Archive

  • Copyright Information: Springer Science+Business Media New York 2000

  • Hardcover ISBN: 978-0-7923-7933-1Published: 31 August 2000

  • Softcover ISBN: 978-1-4613-6948-6Published: 12 October 2012

  • eBook ISBN: 978-1-4615-4337-4Published: 06 December 2012

  • Series ISSN: 0893-3405

  • Edition Number: 1

  • Number of Pages: XIX, 256

  • Topics: Processor Architectures

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