Applied Reconfigurable Computing

Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA

Al-Khatib, Zaid (et al.)

Pages 65-76

Preemptive Hardware Multitasking in ReconOS

Happe, Markus (et al.)

Pages 79-90

A Fully Parallel Particle Filter Architecture for FPGAs

Schwiegelshohn, Fynn (et al.)

Pages 91-102

TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools

Siozios, Kostas (et al.)

Pages 103-114

Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures

Diamantopoulos, Dionysios (et al.)

Pages 117-128

SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs

Sterpone, Luca (et al.)

Pages 129-140

Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties

Hartmann, Philipp A. (et al.)

Pages 141-152

Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable Components

Peña, Xerach (et al.)

Pages 153-164

Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays

Metzner, Michael (et al.)

Pages 167-178

Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-Chip

Gorski, Philipp (et al.)

Pages 179-190

Survey on Real-Time Network-on-Chip Architectures

Hesham, Salma (et al.)

Pages 191-202

Efficient SR-Latch PUF

Habib, Bilal (et al.)

Pages 205-216

Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study

Homsirikamol, Ekawat (et al.)

Pages 217-228

Dual CLEFIA/AES Cipher Core on FPGA

Resende, João Carlos (et al.)

Pages 229-240

An Efficient and Flexible FPGA Implementation of a Face Detection System

Fekih, Hichem Ben (et al.)

Pages 243-254

A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context

Rettkowski, Jens (et al.)

Pages 255-266

A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank

Nakahara, Hiroki (et al.)

Pages 267-279

The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs

Strauch, Tobias

Pages 280-290

A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures

Chattopadhyay, Anupam (et al.)

Pages 293-300

Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA

Rákossy, Zoltán Endre (et al.)

Pages 301-310

A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware

Figuli, Peter (et al.)

Pages 311-320

Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures

Sotiriou-Xanthopoulos, Efstathios (et al.)

Pages 321-330

Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects

Tambara, Lucas A. (et al.)

Pages 331-338

Modular Acquisition and Stimulation System for Timestamp-Driven Neuroscience Experiments

Matias, Paulo (et al.)

Pages 339-348

DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-Based Systems

Chen, Ren (et al.)

Pages 349-356

Acceleration of Data Streaming Classification using Reconfigurable Technology

Giakoumakis, Pavlos (et al.)

Pages 357-364

On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach

Wiersema, Tobias (et al.)

Pages 365-372

Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform

Moghaddam, Mansureh S. (et al.)

Pages 373-382

A Challenge of Portable and High-Speed FPGA Accelerator

Usui, Takuma (et al.)

Pages 383-392

Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array

Moriwaki, Retsu (et al.)

Pages 393-400

Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture

Nolting, Stephan (et al.)

Pages 401-410

Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization

Chtourou, Sonda (et al.)

Pages 411-418

DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost

Castillo, Ernesto (et al.)

Pages 419-426

A Flexible Multilayer Perceptron Co-processor for FPGAs

Aklah, Zeyad (et al.)

Pages 427-434

Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCs

Bueno, Maikon (et al.)

Pages 435-442

Towards Performance Modeling of 3D Memory Integrated FPGA Architectures

Singapura, Shreyas G. (et al.)

Pages 443-450