Applied Reconfigurable Computing

Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA

Pages 65-76

Al-Khatib, Zaid (et al.)

Preemptive Hardware Multitasking in ReconOS

Pages 79-90

Happe, Markus (et al.)

A Fully Parallel Particle Filter Architecture for FPGAs

Pages 91-102

Schwiegelshohn, Fynn (et al.)

TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools

Pages 103-114

Siozios, Kostas (et al.)

Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures

Pages 117-128

Diamantopoulos, Dionysios (et al.)

SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs

Pages 129-140

Sterpone, Luca (et al.)

Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties

Pages 141-152

Hartmann, Philipp A. (et al.)

Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable Components

Pages 153-164

Peña, Xerach (et al.)

Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays

Pages 167-178

Metzner, Michael (et al.)

Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-Chip

Pages 179-190

Gorski, Philipp (et al.)

Survey on Real-Time Network-on-Chip Architectures

Pages 191-202

Hesham, Salma (et al.)

Efficient SR-Latch PUF

Pages 205-216

Habib, Bilal (et al.)

Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study

Pages 217-228

Homsirikamol, Ekawat (et al.)

Dual CLEFIA/AES Cipher Core on FPGA

Pages 229-240

Resende, João Carlos (et al.)

An Efficient and Flexible FPGA Implementation of a Face Detection System

Pages 243-254

Fekih, Hichem Ben (et al.)

A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context

Pages 255-266

Rettkowski, Jens (et al.)

A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank

Pages 267-279

Nakahara, Hiroki (et al.)

The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs

Pages 280-290

Strauch, Tobias

A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures

Pages 293-300

Chattopadhyay, Anupam (et al.)

Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA

Pages 301-310

Rákossy, Zoltán Endre (et al.)

A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware

Pages 311-320

Figuli, Peter (et al.)

Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures

Pages 321-330

Sotiriou-Xanthopoulos, Efstathios (et al.)

Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects

Pages 331-338

Tambara, Lucas A. (et al.)

Modular Acquisition and Stimulation System for Timestamp-Driven Neuroscience Experiments

Pages 339-348

Matias, Paulo (et al.)

DRAM Row Activation Energy Optimization for Stride Memory Access on FPGA-Based Systems

Pages 349-356

Chen, Ren (et al.)

Acceleration of Data Streaming Classification using Reconfigurable Technology

Pages 357-364

Giakoumakis, Pavlos (et al.)

On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach

Pages 365-372

Wiersema, Tobias (et al.)

Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform

Pages 373-382

Moghaddam, Mansureh S. (et al.)

A Challenge of Portable and High-Speed FPGA Accelerator

Pages 383-392

Usui, Takuma (et al.)

Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array

Pages 393-400

Moriwaki, Retsu (et al.)

Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture

Pages 401-410

Nolting, Stephan (et al.)

Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization

Pages 411-418

Chtourou, Sonda (et al.)

DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost

Pages 419-426

Castillo, Ernesto (et al.)

A Flexible Multilayer Perceptron Co-processor for FPGAs

Pages 427-434

Aklah, Zeyad (et al.)

Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCs

Pages 435-442

Bueno, Maikon (et al.)

Towards Performance Modeling of 3D Memory Integrated FPGA Architectures

Pages 443-450

Singapura, Shreyas G. (et al.)

Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL

Pages 451-460

Takamaeda-Yamazaki, Shinya

Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing

Pages 463-474

Hanawa, Toshihiro (et al.)

SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms

Pages 475-486

Lentaris, George (et al.)

Hardware Task Scheduling for Partially Reconfigurable FPGAs

Pages 487-498

Charitopoulos, George (et al.)

SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring

Pages 499-510

Tsoutsouras, Vasileios (et al.)

DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications

Pages 513-518

Mentens, Nele (et al.)

Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective

Pages 519-530

Antonopoulos, Christos (et al.)

Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach

Pages 531-541

Raptopoulos, Andreas (et al.)

COSSIM : A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS Simulator

Pages 542-553

Papaefstathiou, Ioannis (et al.)