Overview
- Emphasises SOC architecture and micro-architecture design with case studies
- Consists of the practical scenarios and issues and helpful to graduate students and professionals
- Covers SOC Design, implementation using VHDL, Synthesis and timing analysis
- Covers key case studies in the generic form for processor, buses, interfaces, memory controllers, DSP and Video controllers
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Table of contents (13 chapters)
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Front Matter
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Back Matter
Keywords
About this book
This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. It covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASIC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.
Authors and Affiliations
About the author
Vaibbhav Taraate is Entrepreneur and Mentor at “1 Rupee S T”. He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur, in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 15 years ofexperience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.
Bibliographic Information
Book Title: Logic Synthesis and SOC Prototyping
Book Subtitle: RTL Design using VHDL
Authors: Vaibbhav Taraate
DOI: https://doi.org/10.1007/978-981-15-1314-5
Publisher: Springer Singapore
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Nature Singapore Pte Ltd. 2020
Hardcover ISBN: 978-981-15-1313-8Published: 30 January 2020
Softcover ISBN: 978-981-15-1316-9Published: 30 January 2021
eBook ISBN: 978-981-15-1314-5Published: 03 January 2020
Edition Number: 1
Number of Pages: XIX, 251
Topics: Circuits and Systems, Control Structures and Microprogramming, Logic Design