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PLD Based Design with VHDL

RTL Design, Synthesis and Implementation

  • Book
  • © 2017

Overview

  • Presents a wealth of practical scenarios and case studies
  • Covers the synthesis and design implementation involved in using programmable ASICs
  • Includes the XILINX and ALTERA PLD architectures and applications
  • Discusses ASIC prototyping and the role of FPGAs for SOC-based design flow
  • Includes supplementary material: sn.pub/extras

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Table of contents (12 chapters)

Keywords

About this book

This book covers basic fundamentals of logic design and advanced RTL design concepts using VHDL. The book is organized to describe both simple and complex RTL design scenarios using VHDL. It gives practical information on the issues in ASIC prototyping using FPGAs, design challenges and how to overcome practical issues and concerns. It describes how to write an efficient RTL code using VHDL and how to improve the design performance. The design guidelines by using VHDL are also explained with the practical examples in this book. The book also covers the ALTERA and XILINX FPGA architecture and the design flow for the PLDs. The contents of this book will be useful to students, researchers, and professionals working in hardware design and optimization. The book can also be used as a text for graduate and professional development courses.

Authors and Affiliations

  • Pune, India

    Vaibbhav Taraate

About the author

Vaibbhav Taraate is Entrepreneur and Mentor at "Semiconductor Training @ Rs.1". He holds a BE (Electronics) degree from Shivaji University, Kolhapur in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his MTech (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 15 Years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high speed VLSI designs, and architecture design of complex SOCs.



Bibliographic Information

  • Book Title: PLD Based Design with VHDL

  • Book Subtitle: RTL Design, Synthesis and Implementation

  • Authors: Vaibbhav Taraate

  • DOI: https://doi.org/10.1007/978-981-10-3296-7

  • Publisher: Springer Singapore

  • eBook Packages: Engineering, Engineering (R0)

  • Copyright Information: Springer Nature Singapore Pte Ltd. 2017

  • Hardcover ISBN: 978-981-10-3294-3Published: 19 January 2017

  • Softcover ISBN: 978-981-10-9836-9Published: 30 April 2018

  • eBook ISBN: 978-981-10-3296-7Published: 13 January 2017

  • Edition Number: 1

  • Number of Pages: XXI, 423

  • Number of Illustrations: 246 b/w illustrations

  • Topics: Circuits and Systems, Electronics and Microelectronics, Instrumentation, Control Structures and Microprogramming

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