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Digital Logic Design Using Verilog

Coding and RTL Synthesis

Authors: Taraate, Vaibbhav

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  • Presents unique ideas to interpret digital logic in the Verilog RTL form
  • Consists of practical scenarios and issues that are helpful to students and professionals
  • Covers key case studies in generic forms and more than 100 practical examples
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eBook 106,99 €
price for India (gross)
  • ISBN 978-81-322-2791-5
  • Digitally watermarked, DRM-free
  • Included format: PDF, EPUB
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover 179,99 €
price for India (gross)
  • ISBN 978-81-322-2789-2
  • Free shipping for individuals worldwide
  • Institutional customers should get in touch with their account manager
  • Covid-19 shipping restrictions
  • Usually ready to be dispatched within 3 to 5 business days, if in stock
Softcover 129,99 €
price for India (gross)
  • ISBN 978-81-322-3838-6
  • Free shipping for individuals worldwide
  • Institutional customers should get in touch with their account manager
  • Covid-19 shipping restrictions
  • Usually ready to be dispatched within 3 to 5 business days, if in stock
About this book

This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design. The practical orientation of the book makes it ideal for training programs for practicing design engineers and for short-term vocational programs. The contents of the book will also make it a useful read for students and hobbyists. 

About the authors

Vaibbhav Taraate is Entrepreneur and Mentor at "Semiconductor Training @ Rs.1". He holds a BE (Electronics) degree from Shivaji University, Kohlapur in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his MTech (Aerospace Control and Guidance)  in 1999 from IIT Bombay. He has over 15 Years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high speed VLSI designs, and architecture design of complex SOCs.

Reviews

“This book presents digital logic design using the hardware description language known as Verilog. … The book will help readers learn digital logic design and become familiar enough with it to work with it further in the future. It is mainly aimed as a textbook for undergraduate students to implement digital logic design in a lab. The book discusses logic design in a well-structured way covering basic to intermediate concepts.” (J. Arul, Computing Reviews, April, 2017)


Table of contents (15 chapters)

Table of contents (15 chapters)

Buy this book

eBook 106,99 €
price for India (gross)
  • ISBN 978-81-322-2791-5
  • Digitally watermarked, DRM-free
  • Included format: PDF, EPUB
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover 179,99 €
price for India (gross)
  • ISBN 978-81-322-2789-2
  • Free shipping for individuals worldwide
  • Institutional customers should get in touch with their account manager
  • Covid-19 shipping restrictions
  • Usually ready to be dispatched within 3 to 5 business days, if in stock
Softcover 129,99 €
price for India (gross)
  • ISBN 978-81-322-3838-6
  • Free shipping for individuals worldwide
  • Institutional customers should get in touch with their account manager
  • Covid-19 shipping restrictions
  • Usually ready to be dispatched within 3 to 5 business days, if in stock
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Bibliographic Information

Bibliographic Information
Book Title
Digital Logic Design Using Verilog
Book Subtitle
Coding and RTL Synthesis
Authors
Copyright
2016
Publisher
Springer India
Copyright Holder
Springer India
eBook ISBN
978-81-322-2791-5
DOI
10.1007/978-81-322-2791-5
Hardcover ISBN
978-81-322-2789-2
Softcover ISBN
978-81-322-3838-6
Edition Number
1
Number of Pages
XXIII, 416
Number of Illustrations
41 b/w illustrations, 226 illustrations in colour
Topics