Authors:
- Highlights a new method which models the interconnects EM reliability in both 3D and circuit layout level
- Combines Cadence and ANSYS softwares to model interconnect reliability of real 3D circuit made up of complete interconnect structures and surrounding materials
- Compares the circuit EM lifetime with different interconnect structures, surrounding materials, circuit layout and process variations
- Includes supplementary material: sn.pub/extras
Part of the book series: SpringerBriefs in Applied Sciences and Technology (BRIEFSAPPLSCIENCES)
Part of the book sub series: SpringerBriefs in Reliability (SBR)
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About this book
Authors and Affiliations
-
, School of Electrical and Electronic Engr, Nanyang Technological University, Singapore, Singapore
Cher Ming Tan
-
Nanyang Technological University, Singapore, Singapore
Feifei He
Bibliographic Information
Book Title: Electromigration Modeling at Circuit Layout Level
Authors: Cher Ming Tan, Feifei He
Series Title: SpringerBriefs in Applied Sciences and Technology
DOI: https://doi.org/10.1007/978-981-4451-21-5
Publisher: Springer Singapore
eBook Packages: Engineering, Engineering (R0)
Copyright Information: The Author(s) 2013
Softcover ISBN: 978-981-4451-20-8Published: 04 May 2013
eBook ISBN: 978-981-4451-21-5Published: 16 March 2013
Series ISSN: 2191-530X
Series E-ISSN: 2191-5318
Edition Number: 1
Number of Pages: IX, 103
Number of Illustrations: 73 b/w illustrations, 2 illustrations in colour
Topics: Quality Control, Reliability, Safety and Risk, Electronic Circuits and Devices, Atomic, Molecular, Optical and Plasma Physics