Overview
- Presents unique view of interpreting FPGA design using SystemVerilog
- Includes practical scenarios and issues useful to professionals
- Provides over 100 practical examples for design and verification
- Covers key case studies in the generic form and design implementation using FPGAs
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Table of contents (15 chapters)
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Front Matter
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Back Matter
Keywords
About this book
Authors and Affiliations
About the author
Vaibbhav Taraate is an entrepreneur and mentor at "Semiconductor Training @ Rs. 1". He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur in 1995. He completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high speed VLSI designs, and architecture design of complex SOCs.
Bibliographic Information
Book Title: SystemVerilog for Hardware Description
Book Subtitle: RTL Design and Verification
Authors: Vaibbhav Taraate
DOI: https://doi.org/10.1007/978-981-15-4405-7
Publisher: Springer Singapore
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Nature Singapore Pte Ltd. 2020
Hardcover ISBN: 978-981-15-4404-0Published: 11 June 2020
Softcover ISBN: 978-981-15-4407-1Published: 11 June 2021
eBook ISBN: 978-981-15-4405-7Published: 10 June 2020
Edition Number: 1
Number of Pages: XXI, 252
Number of Illustrations: 9 b/w illustrations, 95 illustrations in colour
Topics: Circuits and Systems, Control Structures and Microprogramming, Electronics and Microelectronics, Instrumentation, Electronic Circuits and Devices