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Transactions on High-Performance Embedded Architectures and Compilers

Transactions on High-Performance Embedded Architectures and Compilers IV

Editors: Stenström, Per (Ed.)

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About this book

Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This 4th issue contains 21 papers carefully reviewed and selected out of numerous submissions and is divided in four sections. The first section contains five regular papers. The second section consists of the top four papers from the 4th International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The third section contains a set of six papers providing a snap-shot from the Workshop on Software and Hardware Challenges of Manycore Platforms, SHCMP 2008 held in Beijing, China, in June 2008. The fourth section consists of six papers from the 8th IEEE International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS VIII (2008) held in Samos, Greece, in July 2008.

Table of contents (21 chapters)

Table of contents (21 chapters)
  • A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors

    Pages 1-20

    Jahre, Magnus (et al.)

  • Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces

    Pages 21-41

    Vandeputte, Frederik (et al.)

  • Compiler Directed Issue Queue Energy Reduction

    Pages 42-62

    Jones, Timothy M. (et al.)

  • A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors

    Pages 63-83

    Cope, Ben (et al.)

  • Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors

    Pages 84-110

    Khan, Omer (et al.)

Buy this book

eBook 59,49 €
price for Spain (gross)
  • ISBN 978-3-642-24568-8
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Softcover 72,79 €
price for Spain (gross)
  • ISBN 978-3-642-24567-1
  • Free shipping for individuals worldwide
  • This title is currently reprinting. You can pre-order your copy now.
  • The final prices may differ from the prices shown due to specifics of VAT rules
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Bibliographic Information

Bibliographic Information
Book Title
Transactions on High-Performance Embedded Architectures and Compilers IV
Editors
  • Per Stenström
Series Title
Transactions on High-Performance Embedded Architectures and Compilers
Series Volume
6760
Copyright
2011
Publisher
Springer-Verlag Berlin Heidelberg
Copyright Holder
Springer-Verlag GmbH Berlin Heidelberg
eBook ISBN
978-3-642-24568-8
DOI
10.1007/978-3-642-24568-8
Softcover ISBN
978-3-642-24567-1
Series ISSN
1864-306X
Edition Number
1
Number of Pages
XV, 430
Number of Illustrations
222 b/w illustrations
Topics