Reconfigurable Computing: Architectures, Tools and Applications

Systematic Customization of On-Chip Crossbar Interconnects

Pages 61-72

Hur, Jae Young (et al.)

Authentication of FPGA Bitstreams: Why and How

Pages 73-84

Drimer, Saar

Design of a Reversible PLD Architecture

Pages 85-90

Lee, Jae-Jin (et al.)

Designing Heterogeneous FPGAs with Multiple SBs

Pages 91-96

Siozios, Kostas (et al.)

Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations

Pages 97-109

Park, Joonseok (et al.)

Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware

Pages 110-121

Dong, Yazhuo (et al.)

Adapting and Automating XILINX’s Partial Reconfiguration Flow for Multiple Module Implementations

Pages 122-129

Scholz, Rainer

A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions

Pages 130-141

Galuzzi, Carlo (et al.)

Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping

Pages 142-154

Matsuyama, Kazunori (et al.)

The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining

Pages 155-166

Dou, Yong (et al.)

Hardware/Software Codesign for Embedded Implementation of Neural Networks

Pages 167-178

Torres-Huitzil, Cesar (et al.)

Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues

Pages 179-190

Bispo, João (et al.)

About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations

Pages 191-200

Hervé, Nicolas (et al.)

Switching Activity Models for Power Estimation in FPGA Multipliers

Pages 201-213

Jevtic, Ruzica (et al.)

Multiplication over $\mathbb{F}_{{p}^{m}}$ on FPGA: A Survey

Pages 214-225

Beuchat, Jean-Luc (et al.)

A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm

Pages 226-237

Rodríguez-Henríquez, Francisco (et al.)

A Fast Finite Field Multiplier

Pages 238-246

Ferrer, Edgar (et al.)

Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval

Pages 247-258

Chikhi, Rayan (et al.)

Image Processing Architecture for Local Features Computation

Pages 259-270

Díaz, Javier (et al.)

A Compact Shader for FPGA-Based Volume Rendering Accelerators

Pages 271-282

Knittel, Guenter

Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications

Pages 283-292

Lee, Yong-Min (et al.)

FPGA-Accelerated Molecular Dynamics Simulations: An Overview

Pages 293-301

Yang, Xiaodong (et al.)

Reconfigurable Hardware Acceleration of Canonical Graph Labelling

Pages 302-313

Thomas, David B. (et al.)

Reconfigurable Computing for Accelerating Protein Folding Simulations

Pages 314-325

Armstrong, Nilton B., Jr. (et al.)

Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuits

Pages 326-336

Ferlin, Edson P. (et al.)

A Space Variant Mapping Architecture for Reliable Car Segmentation

Pages 337-342

Mota, Sonia (et al.)

A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads

Pages 343-349

Hiramoto, Shinya (et al.)

Searching the Web with an FPGA Based Search Engine

Pages 350-357

McGettrick, Séamas (et al.)

An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner’s Dilemma

Pages 358-364

Yamaguchi, Yoshiki (et al.)

Real Time Architectures for Moving-Objects Tracking

Pages 365-372

Tomasi, Matteo (et al.)

Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller

Pages 373-378

Rocke, Patrick (et al.)

Multiple Sequence Alignment Using Reconfigurable Computing

Pages 379-384

Lima, Carlos R. Erig (et al.)

Simulation of the Dynamic Behavior of One-Dimensional Cellular Automata Using Reconfigurable Computing

Pages 385-390

Weinert, Wagner R. (et al.)