Authors:
- Demonstrates construction of a multi-core machine with pipelined MIPS processor
- Broadens the understanding of RISC machines
- Opens the way to the formal verification of synthesizable hardware for multi-core processors
Part of the book series: Lecture Notes in Computer Science (LNCS, volume 9000)
Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)
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Table of contents (9 chapters)
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Front Matter
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Back Matter
About this book
This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.
The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.
Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.
Keywords
- algebraic specification
- arithmetic logic unit
- automata states
- basic pipelined processor design
- basic sequential mips machine
- cache protocol automata
- finite state machines
- instruction set architecture
- memory embedding
- microprocessor without interlocked pipeline stages
- multi-bank ram
- multi-core
- next pc environment
- pipelining
- scheduling functions
- self destructing hardware
- software conditions
- solving equations
- algorithm analysis and problem complexity
Authors and Affiliations
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Sirrix AG, Saarbrücken, Germany
Mikhail Kovalev
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IBM Germany Research and Development GmbH, Böblingen, Germany
Silvia M. Müller
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Saarland University, Saarbrücken, Germany
Wolfgang J. Paul
Bibliographic Information
Book Title: A Pipelined Multi-core MIPS Machine
Book Subtitle: Hardware Implementation and Correctness Proof
Authors: Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
Series Title: Lecture Notes in Computer Science
DOI: https://doi.org/10.1007/978-3-319-13906-7
Publisher: Springer Cham
eBook Packages: Computer Science, Computer Science (R0)
Copyright Information: Springer International Publishing Switzerland 2014
Softcover ISBN: 978-3-319-13905-0Published: 01 December 2014
eBook ISBN: 978-3-319-13906-7Published: 24 November 2014
Series ISSN: 0302-9743
Series E-ISSN: 1611-3349
Edition Number: 1
Number of Pages: XII, 352
Number of Illustrations: 147 b/w illustrations
Topics: Algorithm Analysis and Problem Complexity, Software Engineering, Computer Hardware, Processor Architectures, Computer Communication Networks, Programming Languages, Compilers, Interpreters