Physical Assurance

This book provides readers with a comprehensive introduction to physical inspection-based approaches for electronics security. The authors explain the principles of physical inspection techniques including invasive, non-invasive and semi-invasive approaches and how they can be used for hardware assurance, from IC to PCB level. Coverage includes a wide variety of topics, from failure analysis and imaging, to testing, machine learning and automation, reverse engineering and attacks, and countermeasures.  

• Hardware Security
• Hardware Assurance
• Hardware Trojan
• Counterfeit Electronics
• IEEE PAINE

• University of Florida, Gainsville, USA

  Navid Asadizanjani, Mir Tanjidur Rahman

• University of Florida, Gainesville, USA

  Mark Tehranipoor

Navid Asadi is an Assistant Professor in the ECE Department at the University of Florida. He investigates novel techniques for IC counterfeit detection and prevention, system and chip level decomposition and security assessment, anti-reverse engineering, 3D imaging, invasive and semi-invasive physical assurance, supply chain security, etc. Dr. Asadi has received several best paper awards from IEEE International Symposium on Hardware Oriented Security and Trust (HOST) and the ASME International Symposium on Flexible Automation (ISFA). He was also winner of D.E. Crow Innovation award from University of Connecticut. He is co-founder and the program chair of the IEEE Physical Assurance and Inspection of Electronics (PAINE) Conference.

M Tanjidur Rahman is a Ph.D. student in Electrical and Computer Engineering at University of Florida, Florida, USA. He received his B.S. and M.S. in Electrical Engineering in 2012 and 2014, respectively, from Bangladesh University ofEngineering and Technology (BUET), Bangladesh. He is a student member of IEEE. He has received the IEEE Best Paper Award at the International Conference on Computer and Electrical Engineering (ICECE), Bangladesh. His current research interests include system and IC level security assessment, hardware assurance, and hardware reverse engineering using physical inspection/attack methods.

Mark Tehranipoor has published over 400 journal articles and refereed conference papers and has given more than 200 invited talks and keynote addresses. In addition, he has 8 patents and has published 11 books and 25 book chapters. He is a recipient of 12 best paper awards and nominations, the 2009 NSF CAREER award, the 2014 MURI award on Nanoscale Security, the 2008 IEEE Computer Society (CS) Meritorious Service Award, the 2012 and 2017 IEEE CS Outstanding Contribution, the 2010 and 2016 IEEE TTTC/CS Most Successful Technical Event for co-founding and chairing HOST Symposium.

He co-founded IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) and served as HOST-2008 and HOST-2009 General Chair and continues to serve as Chair of the Steering Committee for HOST. He also co-founded IEEE Asian-HOST. Further, he co-founded Journal on Hardware and Systems Security (HaSS) and currently serving as EIC for HaSS.

He is also a co-founder of Trust-Hub. He served as associate Editor-in-Chief (EIC) for IEEE Design and Test of Computers from 2012-2014. He is currently serving as an Associate Editor for IEEE Design and Test of Computers, an Associate Editor for JETTA, an Associate Editor for Journal of Low Power Electronics (JOLPE), an Associate Editor for ACM Transactions for Design Automation of Electronic Systems (TODAES), and an Associate Editor for IEEE Transactions on VLSI (TVLSI). He has served as an IEEE Distinguished Speaker and an ACM Distinguished Speaker from 2010-2013. Dr. Tehranipoor is a Fellow of the IEEE, Golden Core Member of IEEE Computer Society, and Member of ACM and ACM SIGDA. He is also a member of the Connecticut Academy of Science and Engineering (CASE).

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