Hardware Architectures for Post-Quantum Digital Signature Schemes

Authors: Soni, D., Basu, K., Nabeel, M., Aaraj, N., Manzano, M., Karri, R.

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  • Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based
  • Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms
  • Enables designers to build hardware implementations that are resilient to a variety of side-channels
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eBook 85,59 €
price for Spain (gross)
  • ISBN 978-3-030-57682-0
  • Digitally watermarked, DRM-free
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Hardcover 103,99 €
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About this book

This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification.  The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs.

  • Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based;
  • Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms;
  • Enables designers to build hardware implementations that are resilient to a variety of side-channels.

About the authors

Deepraj Soni is a Ph.D. student at NYU Tandon School of Engineering. Deepraj works on hardware implementation, evaluation and security of post quantum cryptographic algorithms. He received his M.Tech from the Department of Electrical Engineering, Indian Institute of Technology Bombay (IIT B). His thesis focused on developing a framework for hardware software co simulator and neural network implementation on an FPGA. After graduation, Deepraj worked as a design engineer in the semiconductor division of Samsung and SanDisk. At Samsung, he was responsible for the design and architecture of the image processing IPs such as region segmentation and Embedded CODEC. He was also responsible for communication IPs such as FFT/IFFT, Time & Frequency Deinterleaving and Demapper for canceling the noise. At SanDisk, Deepraj helped in the development of System On Chip (SoC) level design for the memory controller.

Table of contents (10 chapters)

Table of contents (10 chapters)

Buy this book

eBook 85,59 €
price for Spain (gross)
  • ISBN 978-3-030-57682-0
  • Digitally watermarked, DRM-free
  • Included format: EPUB, PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
  • Institutional customers should get in touch with their account manager
Hardcover 103,99 €
price for Spain (gross)
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Bibliographic Information

Bibliographic Information
Book Title
Hardware Architectures for Post-Quantum Digital Signature Schemes
Authors
Copyright
2021
Publisher
Springer International Publishing
Copyright Holder
Springer Nature Switzerland AG
eBook ISBN
978-3-030-57682-0
DOI
10.1007/978-3-030-57682-0
Hardcover ISBN
978-3-030-57681-3
Edition Number
1
Number of Pages
XXII, 170
Number of Illustrations
2 b/w illustrations, 66 illustrations in colour
Topics