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Learning from VLSI Design Experience

Authors: Lee, Weng Fook

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  • Addresses practical design issues and their workarounds
  • Discusses issues such as CDC, crossing clock domain in shift, scan chains across power domain, timing optimization, standard cell library influence on synthesis, DFT, code coverage, state machine
  • Provides readers with an RTL coding guideline, based on real experience
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eBook 106,99 €
price for Spain (gross)
  • ISBN 978-3-030-03238-8
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Hardcover 135,19 €
price for Spain (gross)
  • ISBN 978-3-030-03237-1
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  • Immediate ebook access, if available*, with your print order
  • Usually dispatched within 3 to 5 business days.
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About this book

This book shares with readers practical design knowledge gained from the author’s 24 years of IC design experience. The author addresses issues and challenges faced commonly by IC designers, along with solutions and workarounds. Guidelines are described for tackling issues such as clock domain crossing, using lockup latch to cross clock domains during scan shift, implementation of scan chains across power domain, optimization methods to improve timing, how standard cell libraries can aid in synthesis optimization, BKM (best known method) for RTL coding, test compression, memory BIST, usage of signed Verilog for design requiring +ve and -ve calculations, state machine, code coverage and much more. Numerous figures and examples are provided to aid the reader in understanding the issues and their workarounds.

About the authors

Weng Fook Lee is a distinguished Technical Director at Emerald Systems Design Center with 25 years of IC Design experience. Lee has vast experience in designing with Verilog and VHDL, and is an internationally acknowledged expert in the field of RTL coding and logic synthesis for ASIC/FPGA/SOC. Lee is an expert in synthesizing and tweaking synthesis for performance and low power, leading enhanced methodology to address advanced DFT techniques for VDSM technology, development and deployment of low power standard cell libraries. Lee have lead the development of new architectures and micro-architectures for efficient PMSM motion control ASIC and have developed architectures for AI classification algorithms implementation in ASIC. Lee published “VHDL Coding and Logic Synthesis with Synopsys" with Academic Press Publication, US (ISBN: 0-12-440651-3) in May 2000, "Verilog Coding for Logic Synthesis" with John Wiley Publication, US (ISBN: 0-471-42976-7) in April 2003, “VLIW Microprocessor Hardware Design for ASICs and FPGA” with McGraw Hill Publication, US (ISBN: 978-0071497022) in Aug 2007. Lee is also the inventor and co-inventor of 14 design patents granted by the US Patent and Trademark Office. 

Table of contents (9 chapters)

Table of contents (9 chapters)

Buy this book

eBook 106,99 €
price for Spain (gross)
  • ISBN 978-3-030-03238-8
  • Digitally watermarked, DRM-free
  • Included format: EPUB, PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover 135,19 €
price for Spain (gross)
  • ISBN 978-3-030-03237-1
  • Free shipping for individuals worldwide
  • Immediate ebook access, if available*, with your print order
  • Usually dispatched within 3 to 5 business days.
  • The final prices may differ from the prices shown due to specifics of VAT rules
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Bibliographic Information

Bibliographic Information
Book Title
Learning from VLSI Design Experience
Authors
Copyright
2019
Publisher
Springer International Publishing
Copyright Holder
Springer Nature Switzerland AG
eBook ISBN
978-3-030-03238-8
DOI
10.1007/978-3-030-03238-8
Hardcover ISBN
978-3-030-03237-1
Edition Number
1
Number of Pages
XXIX, 214
Number of Illustrations
86 b/w illustrations, 55 illustrations in colour
Topics

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