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SystemVerilog Assertions and Functional Coverage

Guide to Language, Methodology and Applications

Authors: Mehta, Ashok B.

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  • Covers both SystemVerilog Assertions and Sytem Verilog Functional Coverage language and methodologies
  • Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies
  • Explains each concept in an easy to understand, step-by-step fashion and applies it to a real example
  • Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book
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About this book

This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage.  Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question ‘have we functionally verified everything’.  Written by a professional end-user of both SystemVerilog Assertions and SystemVerilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects.  Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby drastically reducing their time to design and debug.

About the authors

Ashok Mehta is a senior manager in TSMC's CPU/SoC Architecture and Methodology group working on System and 3DIC design projects. In the past, Ashok worked in engineering and management positions at DEC, Data General, Intel and AMCC. He has extensive experience in Design/Verification of complex SoC and Processor devices. He holds nine US patents on ESL and 3DIC designs. Ashok holds a MSEE from University of Missouri.

Table of contents (22 chapters)

Table of contents (22 chapters)

Buy this book

eBook 106,99 €
price for Spain (gross)
  • ISBN 978-1-4614-7324-4
  • Digitally watermarked, DRM-free
  • Included format: PDF, EPUB
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover 135,19 €
price for Spain (gross)
  • ISBN 978-1-4614-7323-7
  • Free shipping for individuals worldwide
  • Immediate ebook access, if available*, with your print order
  • Usually dispatched within 3 to 5 business days.
  • The final prices may differ from the prices shown due to specifics of VAT rules
Rent the eBook  
  • Rental duration: 1 or 6 month
  • low-cost access
  • online reader with highlighting and note-making option
  • can be used across all devices
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Bibliographic Information

Bibliographic Information
Book Title
SystemVerilog Assertions and Functional Coverage
Book Subtitle
Guide to Language, Methodology and Applications
Authors
Copyright
2014
Publisher
Springer-Verlag New York
Copyright Holder
Springer Science+Business Media New York
eBook ISBN
978-1-4614-7324-4
DOI
10.1007/978-1-4614-7324-4
Hardcover ISBN
978-1-4614-7323-7
Edition Number
1
Number of Pages
XXXIII, 356
Topics

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