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Circuit Design for Reliability

  • Book
  • © 2015

Overview

Editors:
  1. Ricardo Reis

    1. Instituto de Informática, Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil

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  2. Yu Cao

    1. School of ECEE, Arizona State University, Tempe, USA

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    You can also search for this editor in PubMed   Google Scholar

  3. Gilson Wirth

    1. Instituto de Informática, Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil

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    You can also search for this editor in PubMed   Google Scholar

  • Provides comprehensive review on various reliability mechanisms at sub-45nm nodes
  • Describes practical modeling and characterization techniques for reliability
  • Includes thorough presentation of robust design techniques for major VLSI design units
  • Promotes physical understanding with first-principle simulations
  • Includes supplementary material: sn.pub/extras

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Table of contents (12 chapters)

  1. Front Matter

    Pages i-vi
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  2. Introduction

    • Ricardo Reis, Yu Cao, Gilson Wirth
    Pages 1-4

  3. Recent Trends in Bias Temperature Instability

    • B. Kaczer, T. Grasser, J. Franco, M. Toledano-Luque, J. Roussel, M. Cho et al.
    Pages 5-19

  4. Charge Trapping Phenomena in MOSFETS: From Noise to Bias Temperature Instability

    • Gilson Wirth, Roberto da Silva
    Pages 21-46

  5. Atomistic Simulations on Reliability

    • Dragica Vasileska, Nabil Ashraf
    Pages 47-67

  6. On-Chip Characterization of Statistical Device Degradation

    • Takashi Sato, Hiromitsu Awano
    Pages 69-92

  7. Compact Modeling of BTI for Circuit Reliability Analysis

    • Ketul B. Sutaria, Jyothi B. Velamala, Athul Ramkumar, Yu Cao
    Pages 93-119

  8. Circuit Resilience Roadmap

    • Veit B. Kleeberger, Christian Weis, Ulf Schlichtmann, Norbert Wehn
    Pages 121-143

  9. Layout Aware Electromigration Analysis of Power/Ground Networks

    • Di-an Li, Malgorzata Marek-Sadowska, Sani R. Nassif
    Pages 145-173

  10. Power-Gating for Leakage Control and Beyond

    • Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
    Pages 175-205

  11. Soft Error Rate and Fault Tolerance Techniques for FPGAs

    • Fernanda Kastensmidt, Ricardo Reis
    Pages 207-221

  12. Low Power Robust FinFET-Based SRAM Design in Scaled Technologies

    • Sumeet Kumar Gupta, Kaushik Roy
    Pages 223-253

  13. Variability-Aware Clock Design

    • Matthew R. Guthaus, Gustavo Wilke
    Pages 255-272
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About this book

This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units.  The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management.

Editors and Affiliations

  • Instituto de Informática, Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil

    Ricardo Reis, Gilson Wirth

  • School of ECEE, Arizona State University, Tempe, USA

    Yu Cao

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