Frontiers in Electronic Testing

Test Resource Partitioning for System-on-a-Chip

Authors: Iyengar, Vikram, Chandra, Anshuman

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  • ISBN 978-1-4615-1113-7
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About this book

Test Resource Partitioning for System-on-a-Chip is about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. Plug-and-play refers to the paradigm in which core-to-core interfaces as well as core-to-SOC logic interfaces are standardized, such that cores can be easily plugged into "virtual sockets" on the SOC design, and core tests can be plugged into the SOC during test without substantial effort on the part of the system integrator. The goal of the book is to position test resource partitioning in the context of SOC test automation, as well as to generate interest and motivate research on this important topic.

SOC integrated circuits composed of embedded cores are now commonplace. Nevertheless, There remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design, and test challenges are a major contributor to the widening gap between design capability and manufacturing capacity. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols.

Test Resource Partitioning for System-on-a-Chip responds to a pressing need for a structured methodology for SOC test automation. It presents new techniques for the partitioning and optimization of the three major SOC test resources: test hardware, testing time and test data volume.

Test Resource Partitioning for System-on-a-Chip paves the way for a powerful integrated framework to automate the test flow for a large number of cores in an SOC in a plug-and-play fashion. The framework presented allows the system integrator to reduce test cost and meet short time-to-market requirements.

Table of contents (10 chapters)

Table of contents (10 chapters)

Buy this book

eBook 83,29 €
price for Spain (gross)
  • ISBN 978-1-4615-1113-7
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover 145,59 €
price for Spain (gross)
  • ISBN 978-1-4020-7119-5
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
  • The final prices may differ from the prices shown due to specifics of VAT rules
Softcover 103,99 €
price for Spain (gross)
  • ISBN 978-1-4613-5400-0
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
  • The final prices may differ from the prices shown due to specifics of VAT rules
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Bibliographic Information

Bibliographic Information
Book Title
Test Resource Partitioning for System-on-a-Chip
Authors
Series Title
Frontiers in Electronic Testing
Series Volume
20
Copyright
2002
Publisher
Springer US
Copyright Holder
Springer Science+Business Media New York
eBook ISBN
978-1-4615-1113-7
DOI
10.1007/978-1-4615-1113-7
Hardcover ISBN
978-1-4020-7119-5
Softcover ISBN
978-1-4613-5400-0
Series ISSN
0929-1296
Edition Number
1
Number of Pages
XII, 232
Topics