VLSI-SoC: Advanced Topics on Systems on a Chip

1. Front Matter

   Pages 1-8

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2. Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies.

   • Gustavo Neuberger, Gilson Wirth, Fernanda Kastensmidt, Ricardo Reis

   Pages 1-16

3. Use of Gray Decoding for Implementation of Symmetric Functions

   • Osnat Keren, Ilya Levin, Radomir S. Stankovic

   Pages 1-16

4. A Programmable Multi-Dimensional Analog Radial-Basis- Function-Based Classifier

   • Sheng-Yu Peng, Paul E. Hasler, David V. Anderson

   Pages 1-20

5. Compression-based SoC Test Infrastructures

   • Julien DALMASSO, Marie-Lise FLOTTES, Bruno ROUZEYRE

   Pages 1-15

6. Parametric Structure-Preserving Model Order Reduction

   • Jorge Fernández Villena, Wil H.A. Schilders, L. Miguel Silveira

   Pages 1-20

7. ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching

   • Marco Paolieri, Ivano Bonesana, Marco Domenico Santambrogio

   Pages 1-20

8. QoS in Networks-on-Chip – Beyond Priority and Circuit Switching Techniques

   • Aline Mello, Ney Calazans, Fernando Moraes

   Pages 1-22

9. Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis

   • Almitra Pradhan, Ranga Vemuri

   Pages 1-20

10. Statistical and Numerical Approach for a Computer efficient circuit yield analysis

    • Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo Reis

    Pages 1-24

11. SWORD: A SAT like Prover Using Word Level Information

    • Robert Wille, Görschwin Fey, Daniel Große, Daniel Große, Stephan Eggersglüß, Rolf Drechsler

    Pages 1-17

12. A new analytical approach of the impact of jitter on continuous time delta sigma converters.

    • J. Goulier, E. Andre, M. Renaudin

    Pages 1-16

13. An adaptive genetic algorithm for dynamically reconfigurable modules allocation

    • Vincenzo Rana, Chiara Sandionigi, Marco Santambrogio, Donatella Sciuto

    Pages 1-18

14. The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm

    • Bassam Mohd, Earl E. Swartzlander Jr., Adnan Aziz

    Pages 1-22

15. System and Procesor Design Effort Estimation

    • Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau

    Pages 1-21

16. Reconfigurable Acceleration with Binary Compatibility for General Purpose Processors

    • Antonio Carlos Schneider Beck, Luigi Carro

    Pages 1-16

17. First Order, Quasi-Static, SOI Charge Conserving Power Dissipation Model

    • Sameer Sharma , L G. Johnson

    Pages 1-23

18. Back Matter

    Pages 1-1

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This book contains extended and revised versions of the best papers that were presented during the fifteenth edition of the IFIP/IEEE WG10.5 International Conference on Very Large Scale Integration, a global System-on-a-Chip Design & CAD conference. The 15th conference was held at the Georgia Institute of Technology, Atlanta, USA (October 15-17, 2007). Previous conferences have taken place in Edinburgh, Trondheim, Vancouver, Munich, Grenoble, Tokyo, Gramado, Lisbon, Montpellier, Darmstadt, Perth and Nice. The purpose of this conference, sponsored by IFIP TC 10 Working Group 10.5 and by the IEEE Council on Electronic Design Automation (CEDA), is to provide a forum to exchange ideas and show industrial and academic research results in the field of microelectronics design. The current trend toward increasing chip integration and technology process advancements brings about stimulating new challenges both at the physical and system-design levels, as well in the test of these systems. VLSI-SoC conferences aim to address these exciting new issues.

• artificial intelligence
• computer
• computer science
• human-computer interaction
• human-computer interaction (HCI)
• modeling
• optimization
• structured analysis
• system modeling

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