The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits
The semi-empirical and compact model approaches
Authors: Jespers, Paul
Free Preview- This book provides a comprehensive overview of design methodologies for Analog Circuits, and includes a MATLAB dedicated toolbox
- Provides useful reference material for professors, students and professionals
- The first 'book' presenting the gm/ID synthesis methodology
- The material and some matters like the graphical construction were presented in conferences and lectures, but no systematic survey was ever published
- An increasing number of papers refer to the gm/ID methodology
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- About this book
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How to determine transistor sizes and currents when the supply voltages of analog CMOS circuits do not exceed 1.2V and transistors operate in weak, moderate or strong inversion? The gm/ID methodology offers a solution provided a reference transconductance over drain current ratio is available. The reference may be the result of measurements carried out on real physical transistors or advanced models. The reference may also take advantage of a compact model. In The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits, we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com allow redoing the tests.
- Table of contents (8 chapters)
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Sizing the Intrinsic Gain Stage
Pages 1-9
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The Charge Sheet Model Revisited
Pages 11-24
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Graphical Interpretation of the Charge Sheet Model
Pages 25-39
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Compact Modeling
Pages 41-66
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The Real Transistor
Pages 67-91
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Table of contents (8 chapters)
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Bibliographic Information
- Bibliographic Information
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- Book Title
- The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits
- Book Subtitle
- The semi-empirical and compact model approaches
- Authors
-
- Paul Jespers
- Series Title
- Analog Circuits and Signal Processing
- Copyright
- 2010
- Publisher
- Springer US
- Copyright Holder
- Springer-Verlag US
- eBook ISBN
- 978-0-387-47101-3
- DOI
- 10.1007/978-0-387-47101-3
- Hardcover ISBN
- 978-0-387-47100-6
- Softcover ISBN
- 978-1-4614-2505-2
- Series ISSN
- 1872-082X
- Edition Number
- 1
- Number of Pages
- XVI, 171
- Topics
