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Frontiers in Electronic Testing

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

Authors: Sachdev, Manoj, Pineda de Gyvez, Jose

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  • Offers broad coverage of topics in test engineering
  • Provides a unique defect-oriented focus of the materials
  • Extensively expanded and updated for this 2nd edition
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  • ISBN 978-0-387-46547-0
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About this book

Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. In Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits state of the art of defect-oriented testing is presented from both a theoretical approach as well as from a practical point of view. Step-by-step handling of defect modeling, defect-oriented testing, yield modeling and its usage in common economics practices enables deeper understanding of concepts.

The progression developed in this book is essential to understand new test methodologies, algorithms and industrial practices. Without the insight into the physics of nano-metric technologies, it would be hard to develop system-level test strategies that yield a high IC fault coverage. Obviously, the work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.

Table of contents (8 chapters)

Table of contents (8 chapters)
  • Introduction

    Pages 1-22

    Sachdev, Manoj (et al.)

  • Functional and Parametric Defect Models

    Pages 23-67

    Sachdev, Manoj (et al.)

  • Digital CMOS Fault Modeling

    Pages 69-110

    Sachdev, Manoj (et al.)

  • Defects in Logic Circuits and their Test Implications

    Pages 111-150

    Sachdev, Manoj (et al.)

  • Testing Defects and Parametric Variations in RAMs

    Pages 151-223

    Sachdev, Manoj (et al.)

Buy this book

eBook 149,79 €
price for Spain (gross)
  • ISBN 978-0-387-46547-0
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover 228,79 €
price for Spain (gross)
  • ISBN 978-0-387-46546-3
  • Free shipping for individuals worldwide
  • Immediate ebook access, if available*, with your print order
  • Usually dispatched within 3 to 5 business days.
  • The final prices may differ from the prices shown due to specifics of VAT rules
Softcover 194,38 €
price for Spain (gross)
  • ISBN 978-1-4419-4285-2
  • Free shipping for individuals worldwide
  • Immediate ebook access, if available*, with your print order
  • Usually dispatched within 3 to 5 business days.
  • The final prices may differ from the prices shown due to specifics of VAT rules
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Bibliographic Information

Bibliographic Information
Book Title
Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Authors
Series Title
Frontiers in Electronic Testing
Series Volume
34
Copyright
2007
Publisher
Springer US
Copyright Holder
Springer-Verlag US
eBook ISBN
978-0-387-46547-0
DOI
10.1007/0-387-46547-2
Hardcover ISBN
978-0-387-46546-3
Softcover ISBN
978-1-4419-4285-2
Series ISSN
0929-1296
Edition Number
2
Number of Pages
XXI, 328
Additional Information
Originally published as volume 10 in this series
Topics

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