Compilation Techniques for Reconfigurable Architectures

Authors: Cardoso, João M.P., Diniz, Pedro C.

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  • Introduces hardware compilation and reconfigurable computing architectures
  • Presents a range of compiler code transformations and mapping techniques focusing on imperative programming languages
  • Bridges the gap between software compilation, hardware compilation, and synthesis domains
  • Brings a number of compilation techniques together into one structured source and includes representative examples of their applications
  • Provides a historical perspective on representative compilations research efforts over the last 15 years
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eBook 118,99 €
price for Spain (gross)
  • ISBN 978-0-387-09671-1
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover 145,59 €
price for Spain (gross)
  • ISBN 978-0-387-09670-4
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
  • The final prices may differ from the prices shown due to specifics of VAT rules
Softcover 145,59 €
price for Spain (gross)
  • ISBN 978-1-4419-3510-6
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
  • The final prices may differ from the prices shown due to specifics of VAT rules
About this book

This book describes a wide range of code transformations and mapping techniques for compiling programs written in high-level programming languages to reconfigurable architectures. While many of these transformations and mapping techniques have been developed in the context of compilation for traditional architectures and high-level synthesis, their application to reconfigurable architectures poses a whole new set of challenges- particularly when targeting fine-grained reconfigurable architectures such as contemporary Field-Programmable Gate-Arrays (FPGAs).

Organized in eight chapters, this book provides a helpful structure for practitioners and graduate students in the area of computer science and electrical and computer engineering to effectively map computations to reconfigurable architectures.

Key Features:

  • Introduces the reader to hardware compilation and reconfigurable computing architectures.
  • Presents a range of compiler code transformations and mapping techniques focusing on imperative programming languages.
  • Allows the reader to bridge the gap between the software compilation and the hardware compilation and synthesis domains.
  • Brings a number of compilation techniques together into one structured source, and includes representative examples of their applications.

  • Provides a historical perspective on representative compilation research efforts over the last 15 years.

Table of contents (8 chapters)

Table of contents (8 chapters)

Buy this book

eBook 118,99 €
price for Spain (gross)
  • ISBN 978-0-387-09671-1
  • Digitally watermarked, DRM-free
  • Included format: PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover 145,59 €
price for Spain (gross)
  • ISBN 978-0-387-09670-4
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
  • The final prices may differ from the prices shown due to specifics of VAT rules
Softcover 145,59 €
price for Spain (gross)
  • ISBN 978-1-4419-3510-6
  • Free shipping for individuals worldwide
  • Usually dispatched within 3 to 5 business days.
  • The final prices may differ from the prices shown due to specifics of VAT rules
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Bibliographic Information

Bibliographic Information
Book Title
Compilation Techniques for Reconfigurable Architectures
Authors
Copyright
2009
Publisher
Springer US
Copyright Holder
Springer-Verlag US
eBook ISBN
978-0-387-09671-1
DOI
10.1007/978-0-387-09671-1
Hardcover ISBN
978-0-387-09670-4
Softcover ISBN
978-1-4419-3510-6
Edition Number
1
Number of Pages
XII, 223
Number of Illustrations
88 b/w illustrations
Topics