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ASIC Design and Synthesis

RTL Design Using Verilog

  • Book
  • © 2021

Overview

Authors:
  1. Vaibbhav Taraate

    1. 1 Rupee S T, Pune, India

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  • Unique to interpretation of ASIC design using Verilog
  • Practical ASIC design scenarios and issues and helpful to professionals
  • More than 150 practical examples for ASIC design, Synthesis and timing analysis
  • Key case studies in the generic form and design synthesis and timing closure for ASIC

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Table of contents (20 chapters)

  1. Front Matter

    Pages i-xxi
    Download chapter PDF

  2. Introduction

    • Vaibbhav Taraate
    Pages 1-12

  3. ASIC Design Flow

    • Vaibbhav Taraate
    Pages 13-26

  4. Let Us Build Design Foundation

    • Vaibbhav Taraate
    Pages 27-48

  5. Sequential Design Concepts

    • Vaibbhav Taraate
    Pages 49-72

  6. Important Design Considerations

    • Vaibbhav Taraate
    Pages 73-84

  7. Important Considerations for ASIC Designs

    • Vaibbhav Taraate
    Pages 85-95

  8. Multiple Clock Domain Designs

    • Vaibbhav Taraate
    Pages 97-112

  9. Low Power Design Considerations

    • Vaibbhav Taraate
    Pages 113-127

  10. Architecture and Micro-architecture Design

    • Vaibbhav Taraate
    Pages 129-138

  11. Design Constraints and SDC Commands

    • Vaibbhav Taraate
    Pages 139-151

  12. Design Synthesis and Optimization Using RTL Tweaks

    • Vaibbhav Taraate
    Pages 153-177

  13. Synthesis and Optimization Techniques

    • Vaibbhav Taraate
    Pages 179-194

  14. Design Optimization and Scenarios

    • Vaibbhav Taraate
    Pages 195-215

  15. Design for Testability

    • Vaibbhav Taraate
    Pages 217-227

  16. Timing Analysis

    • Vaibbhav Taraate
    Pages 229-243

  17. Physical Design

    • Vaibbhav Taraate
    Pages 245-258

  18. Case Study: Processor ASIC Implementation

    • Vaibbhav Taraate
    Pages 259-270

  19. Programmable ASIC

    • Vaibbhav Taraate
    Pages 271-291

  20. Prototyping Design

    • Vaibbhav Taraate
    Pages 293-302
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Keywords

About this book

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.

Authors and Affiliations

  • 1 Rupee S T, Pune, India

    Vaibbhav Taraate

About the author

Vaibbhav Taraate is an entrepreneur and mentor at “1 Rupee S T”. He holds B.E. (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology (IIT) Bombay, India, in 1999. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog , VHDL and SystemVerilog. He has worked with multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis and optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.




Bibliographic Information

  • Book Title: ASIC Design and Synthesis

  • Book Subtitle: RTL Design Using Verilog

  • Authors: Vaibbhav Taraate

  • DOI: https://doi.org/10.1007/978-981-33-4642-0

  • Publisher: Springer Singapore

  • eBook Packages: Engineering, Engineering (R0)

  • Copyright Information: Springer Nature Singapore Pte Ltd. 2021

  • Hardcover ISBN: 978-981-33-4641-3Published: 07 January 2021

  • Softcover ISBN: 978-981-33-4644-4Published: 08 January 2022

  • eBook ISBN: 978-981-33-4642-0Published: 06 January 2021

  • Edition Number: 1

  • Number of Pages: XXI, 330

  • Number of Illustrations: 127 b/w illustrations, 184 illustrations in colour

  • Topics: Circuits and Systems, Control Structures and Microprogramming, Logic Design

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