Overview
- Sizing methodology for analog CMOS circuits
- Low-voltage low-power circuits
- Large signal compact modelling of submicron transistors
- Parameter acquisition
Part of the book series: Analog Circuits and Signal Processing (ACSP)
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About this book
In "The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits", we compare the semi-empirical to the compact model approach. Small numbers of parameters make the compact model attractive for the model paves the way towards analytic expressions unaffordable otherwise. The E.K.V model is a good candidate, but when it comes to short channel devices, compact models are either inaccurate or loose straightforwardness. Because sizing requires basically a reliable large signal representation of MOS transistors, we investigate the potential of the E.K.V model when its parameters are supposed to be bias dependent. The model-driven and semi-empirical methods are compared considering the Intrinsic Gain Stage and a few more complex circuits. A series of MATLAB files found on extras-springer.com allow redoing the tests.
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Table of contents (8 chapters)
Authors and Affiliations
Bibliographic Information
Book Title: The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits
Book Subtitle: The semi-empirical and compact model approaches
Authors: Paul Jespers
Series Title: Analog Circuits and Signal Processing
DOI: https://doi.org/10.1007/978-0-387-47101-3
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer-Verlag US 2010
Hardcover ISBN: 978-0-387-47100-6Published: 04 December 2009
Softcover ISBN: 978-1-4614-2505-2Published: 03 May 2012
eBook ISBN: 978-0-387-47101-3Published: 01 December 2009
Series ISSN: 1872-082X
Series E-ISSN: 2197-1854
Edition Number: 1
Number of Pages: XVI, 171
Topics: Circuits and Systems, Electronics and Microelectronics, Instrumentation, Processor Architectures, Solid State Physics, Spectroscopy and Microscopy